Should "registers" be considered for calculation of FPGA resource consumption

[Altera_Forum]

Hi all, 

 After programming the FPGA EP2S180, I'm now dealing with evaluating its resource consumption. The Dsp Builder Fitter report indicates the utilization ratio for ALUT, memories, PLL, DSP 9-bits and pins elements but only the numbers of registers.  1- I would like to know How many registers there are into the FPGA EP2S180F1020C3?  2- It seems that the registers are parts of the other device features. If so (or if not so), can we take them into account for calculation of the mean FPGA resource consumption?  3- Is there a specific formula for this calculation?  Thanks in advance!

[Altera_Forum]

Did you looked into the Resource usage summary ? 

that reports tells you the truth  Compilation report -> Fitter -> Resource Section -> Resource Usage Summary

[Altera_Forum]

Thank you very much. 

 I was only considering the Dsp Builder compilation report. Now that I load the same project into Quartus II, by following your indications, I can see that there are 147.818 registers for Stratix EP2S180.  I also see there the following lines. Total memory bits 1,540,888 / 9,383,040 ( 16 % ) Total RAM block bits 1,783,296 / 9,383,040 ( 19 % )  How could Total RAM block (a type of memory) bits greater than Total memory bits?

[Altera_Forum]

Total memory bits is how many bits your design uses, Total RAM block bits is how many bits of RAM were used after your memory was mapped and fit into the actual target device. 

 for example if your code inferred a 512 x 17b RAM, it would map to an M9K which is actually 512 x 18b, so your Total RAM block bits would be 512 bits more than Total memory bits because 512 x 1b were "wasted".

[Altera_Forum]

Now it's clear. 

Thank you