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5748 Discussions

Signal problem, MM-SLAVE

Honored Contributor I


My goal is to have a system with a Nios ii processor as a master. The processor should send data to 20 slave units, custom logic, PWM-generators. The data to be sent is just the top value for the PWM-signal. I'm completely new to this, so I've probably done tons of mistakes. Anyhow here's the VHDL code: 


entity PWMtest is 

Port ( 

EXTCLK_I : in STD_LOGIC; -- From the 50MHz clock generator 

PWM_O1, PWM_O2 : out std_logic; 


DATA_ARRIVED : in std_logic; 

DATA_IN : in STD_LOGIC_VECTOR(7 downto 0) 


end PWMtest; 


architecture Behavioral of PWMtest is 


signal clk_50M : std_logic; -- we use this signal for clk 

signal counter : std_logic_vector(7 downto 0) := (others => '0'); 

signal pwm : std_logic; 




clk_50M <= EXTCLK_I;  

PWM_O1 <= pwm; 

PWM_O2 <= NOT pwm; 



begin --process 

if (clk_50M'event and clk_50M='1') then 

if counter < DATA_IN then 

pwm <= '1'; -- the pwm output is high 

else -- the rest of the cycle 

pwm <= '0'; -- the pwm output is low 

end if; 

counter <= counter+1; -- The counter just runs and runs and runs 

end if; 

end process; 


end Behavioral; 


I want to add that VHDL-file in to a component but I have no clue how to get this work. I've tried to read: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf but it's probably not meant to be read by a newbie like me, because I didnt understand much at all. 


Anyhow below have I taken a screenshot of how it looks in my SOPC-builder. What signals should I have if I wanna read the DATA and then perform a PWM signal with data from the nios processor? Would be happy if someone had a tutorial or anything easier than the avalon specifications. 



http://img695.imageshack.us/i/sopco.jpg/ <---- Screenshot of how where I am right now in my attempt to get this to work. 



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