Simple Avalon-MM to onchip memory

[Altera_Forum]

I have been struggling to get a simple Avalon-MM to read from an onchip memory slave. All the examples I've seen have a NIOS connect to the onchip memory which I don't want. I am putting my process logic directly in the master component. 

 I've made sure to configure the same latencies and have matched the Avalon waveform signals between master and slave. I suspect my problem is the memory initialization is not occurring, especially due to the fact that I have enabled the in-system memory content editor feature with an instance id yet whenever I attempt to use the in-system memory content editor and select my device, it says "No instances found". Likewise when I try to use "Update Memory Initialization File", it complains that it "Found no valid Memory Initialization File to process." The full file path to a .hex file is definitely set in the onchip memory component. I created and am managing my .hex file directly in Quartus and have also tried a .mif file with the same results. I've even disabled default initialization and enabled "Use checkered pattern as uninitialized RAM content" with a 0101 pattern.   library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity new_component is port ( avm_m0_address : out std_logic_vector(7 downto 0); -- avm_m0.address avm_m0_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata avm_m0_byteenable : out std_logic_vector(3 downto 0); -- .byteenable avm_m0_write : out std_logic; -- .write avm_m0_chipselect : out std_logic; -- .chipselect avm_m0_writedata : out std_logic_vector(31 downto 0); -- .writedata clock_clk : in std_logic := '0'; -- clock.clk reset_reset : in std_logic := '0'; -- reset.reset read_out : out std_logic_vector(31 downto 0) ); end entity new_component; architecture rtl of new_component is signal chipselect : std_logic := '1'; begin avm_m0_address <= "00000000"; avm_m0_byteenable <= "0001"; avm_m0_write <= '0'; process(clock_clk, chipselect, avm_m0_readdata) begin if rising_edge(clock_clk) then if chipselect = '0' then read_out <= avm_m0_readdata; end if; avm_m0_chipselect <= not chipselect; -- after 20ns; chipselect <= not chipselect; -- after 20.5ns; end if; end process; end architecture rtl; -- of new_component  I have clock_clk, reset_reset, and read_out(7 downto 0) connected to my 50Mhz clock, reset, and 8 LEDs in my top file and all the LEDs light up every time which means they are all staying at '0' as opposed to the all FF's (which should set the LEDs to '1') that I have defined in my .hex file (or the 0101 pattern when onchip is uninitialized).  

[Altera_Forum]

Your master component is not monitoring the waitrequest input signal. All masters have to acknowledge waitrequest, keeping the read or write request on the interface until waitrequest goes high from the interconnect. 

 chipselect is an input for tri-state slaves, not an output for masters. Are you connecting to a tri-state conduit or other off-chip tri-state device?  Does your system successfully generate in Qsys/Platform Designer?  Have you checked the compilation report to verify that the .hex file is associated with and initializing the RAM properly?

[Altera_Forum]

For the memory file (.hex), I have found it picks up if I put it in the project folder, where the QPF/QSF files are located.

[Altera_Forum]

OK, what about my other questions?

[Altera_Forum]

Thank you for the replies. I did originally start with waitrequest without chipselect. My hex file is in the same directory as the QSF/QPF. While digging through the report to see if it mentions the hex file (which it never does) I noticed the LED registers being removed in the optimization step due to a related signal being stuck at GND. I've got to do some more digging to figure out what is causing that or maybe re-create the project from an Avalon-MM master template.