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Simplex RX transceiver design of Arria 10

lambert_yu
Beginner
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Hi all,

      FPGA CHIP : 10ax115n2f45e1sg/ 10ax048h2f34e1hg

      software: quartus 16.0.2 / quartus 18.0.0

      For the same transceiver design, I can pass on the 10ax115n2f45e1sg board but can not pass on the 10ax048h2f34e1hg board, from our hardware engineer, the link on the 10ax048h2f34e1hg will be better than 10ax115n2f45e1sg.

      In our design, we built two simplex RX IP, each have 4 channel; 

      Test reault on two board:

       10ax115n2f45e1sg : transceiver can pass whether there's one /two simplex RX IP in the design;

       10ax048h2f34e1hg : transceiver can pass when there's only one simplex RX IP in the design, but there's only one RX IP can work normally (receive data of some channel of another channel has error)when there's two simplex RX IP in the design. ( All software has tried).

       Same setting for all the IP :

           data rate/ analog setting/ refclk frequency and same TX source.

           

      Difference between the two boards :

         10ax115n2f45e1sg : four channel are continuous for each IP.

          10ax048h2f34e1hg :  One IP  -> one channel from bank 1d, three channels from bank 3e (PIN_v32, PIN_T32, PIN_P32, PIN_m32);

                                                   another IP -> two channels from bank 1d, three channels from bank 1c (PIN_AF32, PIN_AD32, PIN_AB32, PIN_Y32) .

           (refclk located in bank 3e)

      Firstly, I don't know whether there's effect for this kind pin assignment?     

      Secondly, if pin assignment method is no effect,  I think there's no performance difference for these two fpga chip just because they belong to the same series and same speed, right?

       Thirdly, if above two is not the problem, which part will I can detect?

      Could someone give me some advice? (In the attahced, I provide the framwork of our RX design, pin location and IP setting, please check)

       

Brs,

Lambert

 

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