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Single Ended Clk to Differential clock

sa_lahrich
Beginner
389 Views

Hi,

 

I am working on Cyclone V SoC Development Kit, using the High Speed Mezanning Card (HSMC Board).

I have to respect the order of LVDS inputs,  the LVDS input clock must be in the middle of incoming signals. I thought of using  HSMA_CLK_IN_P1 and HSMA_CLK_IN_N1 of the HSMC Board but this pair cannot be connected get a LVDS value on the FPGA. I was wondering if I can use  9 signals of Bank 3 of the HSMC port with the clock in the middle... In other words, use any pair (HSMA_RX_D_PX,HSMA_RX_D_NX) and assign it to this differential clock.

 

Thanks in advance,

 

0 Kudos
1 Solution
EngWei_O_Intel
Employee
374 Views

Hi Samah Lahrich

Thanks for your inquiry. 

Can you help to guide me on the connection you wanted to work on, possibly with a simple diagram?

 

Thanks.

Eng Wei

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2 Replies
EngWei_O_Intel
Employee
375 Views

Hi Samah Lahrich

Thanks for your inquiry. 

Can you help to guide me on the connection you wanted to work on, possibly with a simple diagram?

 

Thanks.

Eng Wei

EngWei_O_Intel
Employee
313 Views

Hi Samah Lahrich

We do not receive any response from you to the previous question that we have asked. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Eng Wei

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