Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,295 Views

Soft ip core design

Hi, 

Basically i want to design one fifo soft ip core which should work any vendor FPGA.(I know so many fifo ip core's are there in market:-P). Already i designed fifo(256x8) using VHDL code and same i tested in one of my project and its working nicely.I just want to know how to make one reliable ip core from RTL code which should work any vendor FPGA(using one common netlist)? i am zero in IP CORE design.Can anyone tell me how to learn basic things about SOFT IP CORE DESIGN? 

 

Thanks and Regards 

Karthi.S
0 Kudos
7 Replies
Altera_Forum
Honored Contributor I
38 Views

A single clock fifo should be no problem. Simple pointers and synthesizable memory is all that is needed. 

 

However when dealing with 2 clocks, several issues come into play. You can use Gray encoding to deal with the pointer issues, but I don't think there is a safe way to synthesize a two port two clock ram. 

 

Pete
Altera_Forum
Honored Contributor I
38 Views

 

--- Quote Start ---  

 

I don't think there is a safe way to synthesize a two port two clock ram. 

Pete 

--- Quote End ---  

 

 

This article suggests that you can, but I think there are slight differences in the templates that XST and Quartus expect so 

you can't have one generic description that will work with all (Altera/Xilinx) devices..... 

 

http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/ 

 

Nial
Altera_Forum
Honored Contributor I
38 Views

The problem will be subtle differences between architectures and tools. The problem with a "generic" fifo is that is will never take full advantage of the architecture of all chips. Usally the best way to get round this is to write a wrapper around the vendor IP with a generic called "CHIP_NAME" or something that then isntatiates the correct vendor IP. This way you can have a generic top level, with a nicely optimised design underneath.

Altera_Forum
Honored Contributor I
38 Views

FWIW: Contrary to a statement in that document, if you do concurrent read and write to the same location with the same clock but without 'old data' configured you can get a mixture of the old and new values - you aren't guaranteed to see one or the other. 

(OK - that was actually two clock mode with both clocks being the same...)
Altera_Forum
Honored Contributor I
38 Views

 

--- Quote Start ---  

FWIW: Contrary to a statement in that document, if you do concurrent read and write to the same location with the same clock but without 'old data' configured you can get a mixture of the old and new values - you aren't guaranteed to see one or the other. 

(OK - that was actually two clock mode with both clocks being the same...) 

--- Quote End ---  

 

 

I'm afraid we are getting diverted from the original post. Basically I need someone to explain me the steps/process/tools involved in designing a IP core and how different it is from a RTL design. Can I get a reference design for the same? 

 

Thanks in advance, 

Karthi. S
Altera_Forum
Honored Contributor I
38 Views

Ip cores are often just heavily tested RTL designs.

Altera_Forum
Honored Contributor I
38 Views

 

--- Quote Start ---  

steps/process/tools involved in designing a IP core and how different it is from a RTL design. 

Karthi. S 

--- Quote End ---  

 

 

An IP core is just a bit of logic that someone else might want to use. 

 

I think with the Xilinx tools you can generate an encrypted netlist, in Altera land you need to become an IP partner to get your 

core encrypted so you can distribute it and Quartus can use it
Reply