Some problem to integrate HDL Import block in Advanced design

[Altera_Forum]

Hi everyone, 

 Im facing a nasty problem, im trying to use the HDL Import block in an Advanced design. I have followed both the instructions about how to interface Standard and Advanced blocksets and how to use the HDL import block.  In particular I saw that all the in/out ports of the file that we want to integrate in the HDL block must be std_logic or std_logic_vector, before they did not so I have just added support signals in order to convert every in the right type.  When I try to run I get the following errors for all the outputs:  "Error reported by S-function 'sInOut' in 'c_fsm/fsm/HDL Output1': This data type is not currently supported."  "An error occurred while propagating data type 'BIT' from 'c_fsm/fsm/HDLImport', output port 1."  I have a two levels design, the lower level with the HDL import block and the HDL In/Out ports, the higher level with the subsystem plus the In/Out ports.  Thanks in advance for the help.

[Altera_Forum]

You can't use the standard blockset inside an advanced blockset design. You can do it the other way around however. See chapter 11 of http://www.altera.com/literature/hb/dspb/hb_dspb_adv_ug.pdf (http://www.altera.com/literature/hb/dspb/hb_dspb_adv_ug.pdf).

[Altera_Forum]

--- Quote Start ---  You can't use the standard blockset inside an advanced blockset design. You can do it the other way around however. See chapter 11 of http://www.altera.com/literature/hb/dspb/hb_dspb_adv_ug.pdf (http://www.altera.com/literature/hb/dspb/hb_dspb_adv_ug.pdf).  --- Quote End ---    Actually I have already followed that chapter, what I wanted to do is to interface my datapath designed with the Advanced blockset (subsystem1) with a finite state machine that I have in a file .vhd (subsystem2). In the subsystem2 I have just the block HDL Import.  Is it possible what I want to do?  If not, would you advice to me a way to implement an FSM with the Advanced blockset? (I didnt get why there are not blocks that let design an FSM within the Advanced blockset...)  Thanks again

[Altera_Forum]

--- Quote Start ---  Actually I have already followed that chapter, what I wanted to do is to interface my datapath designed with the Advanced blockset (subsystem1) with a finite state machine that I have in a file .vhd (subsystem2). In the subsystem2 I have just the block HDL Import.  Is it possible what I want to do?  --- Quote End ---    You could route all the inputs to the state machine out of the advanced part of the design as outputs into state machine and then route the results back in. If the state machine is essentially in the middle of your datapath then this might cause problems if the signals go through the same ChannelIn/ChannelOut blocks as the main input/output of the system.  In this case you could try making the inputs/outputs go through GPIn/GPOut blocks although this can often lead to simulation mismatches in Modelsim.  Without seeing a design it's difficult to say anything more.

[Altera_Forum]

--- Quote Start ---  You could route all the inputs to the state machine out of the advanced part of the design as outputs into state machine and then route the results back in. If the state machine is essentially in the middle of your datapath then this might cause problems if the signals go through the same ChannelIn/ChannelOut blocks as the main input/output of the system.  In this case you could try making the inputs/outputs go through GPIn/GPOut blocks although this can often lead to simulation mismatches in Modelsim.  Without seeing a design it's difficult to say anything more.  --- Quote End ---    Mmm ok, but right now I was just trying to run the FSM and it is not working showing the errors of my first post, I have from the lowest level of subsystem to the highest:  1- HDL Import block 2- HDL In/Outputs with Device block 3- In/Output ports (IO & bus) with simulink inputs + scope  And what about designing an FSM with the Advaced blockset, is that possible?

[Altera_Forum]

--- Quote Start ---  "Error reported by S-function 'sInOut' in 'c_fsm/fsm/HDL Output1': This data type is not currently supported."  "An error occurred while propagating data type 'BIT' from 'c_fsm/fsm/HDLImport', output port 1."  --- Quote End ---    This sounds a little bit like you have the HDL Import block feeding an HDL Output block. This is definitely wrong. If anything an HDL Import block should feed an HDL Input block.  HDL Input blocks should be connected to input ports in the blackbox subsystem. (In this case your advanced blockset design is the blackbox subsystem). HDL Output blocks should be connected to the outport ports of this subsystem. There should be no other standard blockset blocks in this subsystem at all.  You could design an FSM with Advanced blockset but it can be quite tricky. It really depeds how complicated it is.

[Altera_Forum]

--- Quote Start ---  This sounds a little bit like you have the HDL Import block feeding an HDL Output block. This is definitely wrong. If anything an HDL Import block should feed an HDL Input block.  --- Quote End ---   Hmm, please let me understand if I got what you are saying, so if I want to use this HDL Import block the "connecting chain" would be like:  Simulink Input -> In blocks (IO&bus) -> GPin , HDL Import , GPout -> HDL Input -> ? , Scope  The arrow means going deeper as level of subsystem, the coma means that those blocks are living in the same subsystem. Im sure there is something wrong in that chain :D , could you please write down to me the right one?    --- Quote Start ---  HDL Input blocks should be connected to input ports in the blackbox subsystem. (In this case your advanced blockset design is the blackbox subsystem). HDL Output blocks should be connected to the outport ports of this subsystem. There should be no other standard blockset blocks in this subsystem at all.  --- Quote End ---   Cool, Im ok with that!    --- Quote Start ---  You could design an FSM with Advanced blockset but it can be quite tricky. It really depeds how complicated it is.  --- Quote End ---   1- I would love to know how to do that! 2- Could it be possible to use StateFlow blocks in Advanced systems to design FSM? 3- At the end if one must use an FSM how do you advice to do that?  Thanks!!!

[Altera_Forum]

--- Quote Start ---  Hmm, please let me understand if I got what you are saying, so if I want to use this HDL Import block the "connecting chain" would be like:  Simulink Input -> In blocks (IO&bus) -> GPin , HDL Import , GPout -> HDL Input -> ? , Scope  The arrow means going deeper as level of subsystem, the coma means that those blocks are living in the same subsystem. Im sure there is something wrong in that chain :D , could you please write down to me the right one?  --- Quote End ---    No if anything it should be:  Simulink Input, In blocks (IO&bus), HDL Import -> HDL Input -> GPin, <datapath> , GPout -> HDL Output -> Out blocks (IO&bus) , Scope    --- Quote Start ---   You could design an FSM with Advanced blockset but it can be quite tricky. It really depeds how complicated it is.  1- I would love to know how to do that! 2- Could it be possible to use StateFlow blocks in Advanced systems to design FSM? 3- At the end if one must use an FSM how do you advice to do that?   --- Quote End ---    1. To build a state machine out of advanced blocks, you would have to use the primitive blocks that are there. This means managing the state transitions yourself. It's not something I've done much on. 2. StateFlow blocks are not supported by either Standard or Advanced blockset. 3. If your FSM is only controlled by the inputs to the top level system and have no direct feedback from your datapath, then it probably easiest to build the statemachine. If you want lots of feedback into your state machine from your datapath then it may be easier to build it using advanced blocks.

[Altera_Forum]

--- Quote Start ---  No if anything it should be:  Simulink Input, In blocks (IO&bus), HDL Import -> HDL Input -> GPin, <datapath> , GPout -> HDL Output -> Out blocks (IO&bus) , Scope  --- Quote End ---    Cool, thanks!! That works perfectly!!  I have just a curiosity how is Simulink able to run his functional simulation by using the HDL Import? I mean how is it able to interpret the VHDL code?

[Altera_Forum]

--- Quote Start ---  I have just a curiosity how is Simulink able to run his functional simulation by using the HDL Import? I mean how is it able to interpret the VHDL code?  --- Quote End ---    DSP Builder uses Quartus to parse the HDL and generate a netlist. DSP Builder then simulates that net list. In many ways it's quite similar to the way Modelsim works.