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Stratix 10 Native PHY PMA register details for reverse serial loopback

HBhat2
New Contributor II
204 Views

Hi,

Board: Stratix 10 SoC Kit- L-tile.

I am accessing PMA registers to configure the transceiver pairs (GXT) in reverse serial loopback mode. 

As per the transceiver user guide: 

{0x11D[0], 0x132[5:4], 0x137[7], 0x144[1], 0x142[4]} : 

6'b000000 - Disable reverse serial loopback
6'b100101 - Enable pre-CDR reverse serial loopback
6'b001010 - Enable post-CDR reverse serial loopback

I have written the RTL to update this read modified write logic as well.

Also, I have carried out one testing. Here, I have configured the required transceiver pairs to Reverse serial loopback mode using "Transceiver Toolkit"

Then, I simply read the registers using Av-MM ports of Transceivers. I am observing the values different from the one which is mentioned in the userguide.

I am observing {0x11D[0], 0x132[5:4], 0x137[7], 0x144[1], 0x142[4]} = 6'b000110 instead of the values mentioned in the user guide. 

So, Please clarify which is the correct configuration data to configure transceivers in reverse serial loopback  mode (both pre-CDR & Post CDR)

With Regards,

HPB

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4 Replies
Deshi_Intel
Moderator
187 Views

Hi HPB ,


Based on user guide doc table A.4.4 - Loopback setting table :

  • Encodings {0x11D[0], 0x132[5:4],0x137[7], 0x144[1], 0x142[4]}
  • 6'b000000 - Disable reverse serial loopback
  • 6'b100101 - Enable pre-CDR reverse serial loopback
  • 6'b001010 - Enable post-CDR reverse serial loopback


However, there is also separate note on page 393 that mentioned GXT channel doesn't support reverse serial loopback as well


Therefore, don't try it on GXT channel else it may end up with weird result as seen by you.


Thanks.


Regards,

dlim


HBhat2
New Contributor II
185 Views

Hi dlim,

I am aware of reverse serial loopback not supported in GXT speed (More than 17Gbps).

What I mentioned previously is the transceiver channel whichever I am using is GXT capable (In L-tile all channels can not support upto 26Gbps). But, the channels are configured @10.3125Gbps rate. 

 

With Regards,

HPB

Deshi_Intel
Moderator
181 Views

Hi HPB,


Let's put a side the issue with toolkit for now, user guide doc table A.4.4 - Loopback setting table is correct.

  • I traced back some Intel internal test record and someone did verified reverse serial loopback with setting in table A.4.4 before.


Just wonder did you manage to test out on hardware board to see whether there is actual data appear on Tx channel once you supply data to Rx channel and enable the reserve serial loopback ?

  • Also try to use latest Quartus version if possible to avoid any potential known issue in earlier Quartus version.


My concern is still on the GXT channel since Quartus declare no support on GXT channel, would you be able to try out on physical GX channel

  • Meaning NativePHY IP set "channel type" to GX, not GXT
  • Physically you are using GX channel like channel 2 or 5 within one transceiver bank, avoid channel [4,3,1,0]


Thanks.


Regards,

dlim


Deshi_Intel
Moderator
168 Views

Hi HPB,


I have not hear back from you for sometime. I hope you have found out the issue with the loopback setting as the address mapping looks correct.


For now, I am setting this case to closure as I can't let the case idle for too long.


Feel free to post new forum thread if you would like to continue the debug discussion in future.


Thanks for your understanding.


Regards,

dlim


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