Stratix 10M DIB timing constraints

[User1573261788318367]

Hi all,

I have a 20 MHz DUT clock and 400 MHz DIB clock in my design (split across the U1 and U2 dies of the Stratix 10M). In the timing report I"m seeing a lot of violations between these two domains, going between the DUT and DIB clock domains. I am running in async TDM 4:1 mode. Is it OK to declare all of these as false path?

set_false_path -from [get_clocks {u0|iopll_0|iopll_0_dut_clk}] -to [get_clocks {u0|iopll_0|iopll_0_dib_clk}]

[Kenny_Tan]

Does your DUT stand for test bench?

1) If yes, you do not need to include testbench to your design

2) If no, you may consider change your design to either

a) clock enable signal https://www.fpga4student.com/2017/08/how-to-generate-clock-enable-signal.html

b) add additional pipelines to close the timing.

c) set_multicycle_path

setting the false path means that you want the Quartus totally ignore those cross clock domain. I would not recommend it unless you are sure it won't break the functionality.

[User1573261788318367]

Hi KennyT,

It is not a testbench. This is a special-purpose IP that's connected to the Stratix 10 PCIe HIP. Our design is spread across both dies of the Stratix 10M FPGA, and these dies talk to each other through the die-interconnect bridge ("DIB").

I posted this question specifically to ask about item 2c in your response. The DIB is an Intel-provided hard IP, and I don't know whether I can safely set false_path between the DUT clock and the DIB clock. The implementation of the DIB is a black box to me.

[Kenny_Tan]

What you can do is look into the design example/reference design how they write the PCIE constrain. From there, you should be able to determined which to used in the above.

[Kenny_Tan]

any update?