Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
868 Views

Stratix IV DDR3 memory controller with Unify : simulation not working

Hello. 

 

I have a problem using DDR3 memory controller with Unify on Stratix IV. 

I use modelsim SE 6.5d or 10.0. 

 

My problem is that the controller is not working both with my design and Altera reference design. 

 

After issuing reset,The PLL locked. Then I am waiting for mem_resetn on DDR3 interface to be deasserted but nothing happen after 5 ms. 

 

On DDR3 interface, clock is running at the good frequency after controller reset deassertion. 

 

During simulation I have warnings which seems not normal for me but I don't know why they appears. 

For example, Modelsim display warnings as : 

# ** warning: ../../../../../fpgavendorip/altera/sgxdk_ddr3/ddr3_ctrl/ddr3_ctrl_example_design_fileset/example_project/ddr3_ctrl_burst_boundary_addr_gen.sv(63): [svchk] - some checking for conflicts with always_comb and always_latch variables not yet supported. run vopt to provide additional design-level checks. 

 

or 

# ** warning: (vsim-3015) ../../../../../fpgavendorip/altera/s4gxdk_ddr3/ddr3_ctrl/ddr3_ctrl/ddr3_ctrl_0002_controller_phy.sv(486): [pcdpc] - port size (4 or 4) does not match connection size (1) for port 'afi_doing_read'. 

I also have the following error : 

# error: cannot read ddr3_ctrl_0002_sequencer_rom_ddr3.hex. 

 

Thanks for your help. 

Regards. 

Olivier.
0 Kudos
7 Replies
Altera_Forum
Honored Contributor I
73 Views

How long have you run the simulation for? The memory initialization and calibration can take quite a while before you see any activity on the internal interfaces. Check for the local_init_done signal being asserted and make sure you've set the calibration setting in SOPC builder to fast or skip calibration.

Altera_Forum
Honored Contributor I
73 Views

I run the simulation during 5 ms with the skip calibration enabled. 

I also check the local_init_done. It os used as a enable for my application on the Avalon interface. It is because I never see my application running that I worried about the DDR3 interface. 

I use the controller as a stand alone without SOPC builder. 

I wonder why the DDR restn signal is still active after a so long time. The calibration can not be done if the DDR device is in reset state !?! 

 

I feel my problem come from warning. These mismatched connexions seem not normal for me, as the non-loading of the hex file for the sequencer. 

 

But I don't find how to solve them. 

Does anyone experienced the same warnings/error than I have ? 

 

Regards.
Altera_Forum
Honored Contributor I
73 Views

Hello: 

 

I want to ask that whether you have solved this problem. I am using the DDRIII controller IP of stratix III. 

i use modelsim 6.5 to simulate and my simulation is also not working. 

my local diver signals for the ddriii controller are all right,for example:local_write_req,local_burstbegin,local_ready math the requests ,but the ddriii interface are not working. 

thanks for your help
Altera_Forum
Honored Contributor I
73 Views

Hi, 

 

I'm experiencing what appears to be the same problem on a Cyclone V using the DDR3 hard memory controller.  

 

Based on dates, I assume that everyone above has found a solution. What is the solution?? It feels like the controller is being held in reset somehow but it's not obvious.  

 

Any help appreciated.
Altera_Forum
Honored Contributor I
73 Views

In case anyone ever runs into this, there is a memory initialization hex file that wasn't being properly read into the simulation. This caused the sequencer to read out all 0's from its init memory, which controls the DDR pins at the start of time (and nitialization couldn't complete).

Altera_Forum
Honored Contributor I
73 Views

Hi All, 

 

I also had problems with the DDR3 uniPhy for stratixV. when i simulated the design with the Aldec- Active-HDL9.1 simulator i noticed that the initialization/calibration never starts. 

My solution for this issue was to copy the *.hex files from the "...\design_name\design_name_sim\design_name\" folder  

to the "..\SRC\" folder . 

This folder is where Active-HDL searches for hex files when they are aplicable to the design. 

 

and this worked for me!!! 

 

So, i guess you can do something similar in modelsim. 

 

I hope this helps to those of you who are still stuck. 

regards 

Dror.
Altera_Forum
Honored Contributor I
73 Views

I have seen this too. It is a bit messy to use their simulation IPs. The code of the IP assumes you have your RTL/IP files in the same directory you simulate, what I believe is a mistake. I then change one file to point to the correct location. This is a problem as every time the IP is regenerated the code has to be repatched, but at least we keep some kind of order. 

 

After the IP files have been generated we generate the simulation files by: 

From the directory .../mem_ip/simulation/ use quartus_sh -t generate_sim_verilog_example_design.tcl 

 

And then edit the file syn/sm01/mem_ip_sim/mem_ip/mem_ip_s0.v and then add IPHEXDIR to the parameters: INIT_FILE, AC_ROM_INIT_FILE_NAME, INST_ROM_INIT_FILE_NAME. 

At the end each has to be: ({`IPHEXDIR, “.......”}). 

 

Then when I simulate I pass a define via the command line for IPHEXDIR. This could have been statically written but with it dynamic makes it easier to move the code around in case we need to. 

 

For the command line, I simply copied out the libraries defined in the cadence shell script. Then we run it in our environment.
Reply