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RWitt
Beginner
1,571 Views

Stratix PCIe hard-core - does it really support 256 non-posted tags?

The Stratix PCIe hard core mentions support for 256 tags, is that true? The A10 core used to say it supported 256 then over time the documentation was updated to specify a max of 64 when extended tag support was enabled.

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8 Replies
Nathan_R_Intel
Employee
80 Views

Hie,

 

You need to refer to the available document for each device and interface type on number of tags supported for non-posted request.

As an example, refer to :

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-a10-pcie-avm...

(Refer to Table 1-2)

 

For Arria 10 , the number of tags supported for non-posted request is 256 for AVST interface, 8 for AVMM, 16 or 256 for AVMM-DMA.

 

Regards,

Nathan

Nathan_R_Intel
Employee
80 Views

Please refer to the latest user Guide, it has more complete information. Ignore my previous post. It was based on an older document.​

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm_dma.pdf

 

 

ignore --> "For Arria 10 , the number of tags supported for non-posted request is 256 for AVST interface, 8 for AVMM, 16 or 256 for AVMM-DMA."

RWitt
Beginner
80 Views

Sure, but the earlier A10 documentation said 256 as well, and still does for the Avalon-ST interface in that doc you just shared. And for the A10 you find later in the doc that it only supports 64, as well as finding out in Platform Designer. Since I have not tried to load the design in a Stratix environment I was hoping to get an "inside" answer versus a documentation answer.

 

On the A10 side: Interesting that the Avalon-MM DMA says support for 256 tags where as the ST is limited to 64. Is that due to the tag support moving out to the DMA bolt-on block/IP? That would answer another post I have: whether that support can be moved to the application interface.

 

Update: 12/04/18 - though not intending on using it - I built the Avalon-MM DMA example design and see that the DMA logic manages the tags, and appears to support 256. In another old post from someone else I asked if the tag processing could be moved to the application layer, in that DMA design it is - so if we were to do that, how do we tell the HIP to not check the tag value (all of the documentation says that the HIP will not process non-posted transactions whose tag value is above the value programmed - and for Avalon-ST designs the maximum value is 64 (63 technically))???

Nathan_R_Intel
Employee
80 Views

Hie,

 

Yes the document was updated for Arria 10 to indicate the amount of tags supported for AVST is changed from 32/64/128/256 to 32/64. This is indicated in the document revision history. This was a documentation error.

Even the latest document still has an error showing 128 and 256 in Table 3. Only Table 16 has been updated to show the correct values.

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf

 

I have filed a request to update our document to remove this. Anyway for Arria 10 AVST, the amount of tags supported is  32 or 64 as you can observe in PCIe IP in Platform Designer.

 

My apologies but currently we do not support moving the tag processing to the application layer totally. Hence, from Intel side we do not have a guideline on how you can achieve this.

 

 

Regards,

Nathan

 

 

RWitt
Beginner
80 Views

Thanks for the reply Nathan. Another question though, as I mentioned above, when I read and then configured the core for the Avalon-MM DMA I was able to select support for 256 tags, and it appeared that the soft DMA logic was managing the tags.

That MM design appears to have the same ST interface to the embedded PCIe HardCore, how can they support 256 tags?

Nathan_R_Intel
Employee
80 Views

 

 

 

Yes the document was updated for Arria 10 to indicate the amount of tags supported for AVST is changed from 32/64/128/256 to 32/64. This is indicated in the document revision history. This was a documentation error.

Even the latest document still has an error showing 128 and 256 in Table 3. Only Table 16 has been updated to show the correct values.

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf

 

I have filed a request to update our document to remove this. Anyway for Arria 10 AVST, the amount of tags supported is 32 or 64 as you can observe in PCIe IP in Platform Designer.

As for Stratix 10 AVST, the amount of tags supported is 256. The option in PCIe IP in Platform Designer is to enable "PF0 Support Extended Tag Field"

 

My apologies but currently we do not support moving the tag processing to the application layer totally. Hence, from Intel side we do not have a guideline on how you can achieve this.

Regards,

Nathan

Nathan_R_Intel
Employee
80 Views

Hie,

 

As mentioned in other thread, 256 tags cannot be supported in AVST.

Hence, I will not be able to get into details how 256 supported in AVMM-DMA due to proprietary reasons.

 

Regards,

Nathan

RWitt
Beginner
80 Views

I'm asking for the Arria 10 PCIe core based on the AVMM-DMA (not the Stratix).

Those "proprietary reasons" need to be resolved on the customer's behalf for both the Arria and the Stratix- when we are looking to support 50Gbps on the Arria (two ports), and 100Gbps on the Stratix - being limited to 64 tags is "not" acceptable - Intel must get over their proprietary issues and support 256 tags. If there is an issue in the core then at least allow the application layer to support them externally - that is what I've done with the Synopsys core in the past (ASIC) - years ago, Intel is years behind... and I'll leave it at that...

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