Stratix V PCIe HIP not supporting Avalon MM Gen3 x8 I/F

[Altera_Forum]

Can anyone say why ? 

 I have a single EP design using Avalon MM interconnect and across Cyclone IV, Arria V and Stratix V and I want to support Gen3 X1, X4 and X8 on the Stratix V card ... This is a problem to switch to Avalon ST interconnect for one design point ....  Any ideas on how to get around this ?  Thanks, Bob.

[Altera_Forum]

Instead of rely on assign gen3_speed = tl_cfg_tl_cfg_sts[32:31] == 2'b11;  

how about you use Signaltap II to monitor current_speed[1:0] and see if the link is really train-up to gen3. The following encodings are defined: - 2b’00: Undefined - 2b’01: Gen1 - 2b’10: Gen2  2b’11: Gen3