FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Frame Reader IP core

Honored Contributor II

Hi everyone, 


I'm using the DE1-SoC board from Terasic and I am attempting to display some image. 


Currently I am using a Qsys system that contains a NIOS II and the Clocked Video Ouput IP core. 

All external connections are fine, since I have used the Test Pattern Generator to stream data to the Clocked Video Output core, and I get a nice image on my VGA screen. 

I also have an SDRAM controller connected to the 64 MB SDRAM. This is also working fine. 


Now I am trying to connect the Frame Reader IP core to read pixels from the SDRAM and create a stream to the Clocked Video Output. 


I am having many troubles with the Frame Reader IP core. The documentation here (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_vip.pdf) is quite... incomplete, if you ask me. 


I have tried several configurations, since I was thinking it might be due to memory latency problems. 


- placing the frame in onchip memory and making the frame reader the only master of this memory 

- tried with many different settings of the Frame Reader IP core. 

- tried with many different settings of the Frame Reader IP core registers. 


What works now is that the Frame Reader IP core only display the last pixel of my memory reserved for the image. 

The whole screen takes the value of this pixel. This is the closest thing to a working frame reader ip core I could get. Otherwise I only get a black screen. 


When I connect the interrupt sender and IRQ to the NIOS II, then the frame readers breaks down completely, no matter what setting I choose. Also the core does not generate any interrupts even though I have enabled them in the control registers. 


If anyone has a hint where to look now I'd be much obliged. 


Thanks in advance!
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Honored Contributor II

I have solved the problem. 


It was as expected a problem with the memory latency. 


On my SDRAM controller are now: 


- the NIOS II data and instruction master 

- the Frame Reader master 


However, I had to change the arbitration for the Frame Reader to give it more priority. 


I found this in this (https://www.altera.com/en_us/pdfs/literature/tt/tt_nios2_system_architect.pdf) document. 


Right click in the Systems Contents view in Qsys. 

Check Show Arbitration Shares. 


The priority is on the point where you connect different interfaces as a number. Default is 1. 

I changed the frame reader priority to 50. 


There are still some artifacts, but that should be easy to fix. 


I hope it can also help someone else.
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