Stratix10 P-Tile PCIe Hot Reset

[anat]

Hi,

How does the application get the hot reset information when P-Tile IP configured as EP.

[anat]

Any updates?

[ventt]

Hi anat,

Thanks for reaching out.

Allow me some time to investigate your issue. I shall come back to you with the findings.

Thanks.

Best Regards,

Ven

[ventt · Accepted solution]

Hi anat,

My apology for the delayed response.

You can read the Bridge Control Register bit location 6, Secondary Bus Reset register, to obtain the information on hot reset on the host side. Alternatively, you can enable the Hard IP Reconfiguration interface when configuring the PCIe device in Endpoint mode, and obtain the hot reset information via this interface from the FPGA side.

You may refer to the documents:

1. PCIe Base Specification Rev. 4.0 Section 7.5.1.3.13 Bridge Control Register: http://www.pcisig.com/

2. P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683059/24-3/hard-ip-reconfiguration-interface.html

I hope this helps.

Thanks.

Best Regards,

Ven

*Kindly take note that 31 Mar and 1 Apr 2025 are national public holidays, please expect a delay in response.

[ventt]

Hi anat,

May I know if you have further questions on this thread?

Thanks.

Best Regards,

Ven

[ventt]

Hi anat,

Good day.

Please let me know if you have further inquiries in this thread.

Thanks.

Best Regards,

Ven

[anat]

Thanks Ven

[ventt]

Hi anat,

Thank you for confirming that your questions have been addressed. I'm glad that this has been helpful.

I now transition this thread to community support. If you have a new question, feel free to open a new thread to get support from Altera experts. 

Thanks.

Best Regards,

Ven