how to expand the pcie rx completion buffer size?

[vincent_lin]

As the documetion says, it is critical to monitor the available RX completion buffer entries to prevent overflow by excessive Non-Posted requests. However, the current RX completion buffer in our IP core has limited capacity - providing only 1,444 credits for Completion Data (CplD), which translates to approximately 1.4μs of buffer time at 500MHz clock frequency with a 512-bit data width. This constraint significantly impacts our ability to maintain optimal outstanding request performance. Could you suggest potential methods to increase the throughput of Non-Posted requests within the current system constraints?

[Wincent_Altera]

Hi ,

May I know which document that you are referring to ?
What is the device/design ? just to ensure that we are looking at the same page.

Regards,

Wei Chuan

[vincent_lin]

Hi,

    The document is  P-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide, and our device is AGFB023R25A2E2V,

 the suggestion of How to send NP Requestes as follow,

the completion buffer size as follow

 

[Wincent_Altera]

Hi,

I do a deep check on that, unfortunately NP transactions mentioned in the user guide is the maximum. 
If this features is strictly needed and you have strong business justification, I suggest to talk to your local Distributor FAE to file a feature request ticket.

Please accept my apology for cannot help so much on this.

Regards,
Wincent_Altera

[Wincent_Altera]

Hi,

I wish to follow up with you about this forum case.

Do you have any further questions on this matter ? Else do I have your permission to close this IPS ticket ?

Regards,

Wincent_Altera

[vincent_lin]

Hi,

No further questions. You may close this case now.

Regards