Stratix10 PAM4 FPGA

[Lily1234]

Dear Sir/ Madam, 

I understand Intel Stratix 10 board can receive a PMA4 signal (Data rate from 2 Gbps to 57.8 Gbps). The I/O standard is LVPECL, the below picture is the LVPECL 's specification and shows the VICM，VID.  But I still feel confused. PAM4 signals have 4 voltage levels. Could you please further explain the specifics for each level?

For example,  the demands for eye width, eye height, eye nonlinearity, and SNDR(Signal to noise and dispersion ratio)  .

Below is the introduction of LVPECL.  A full document can be found in the below link (page 27)

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/s10_datasheet.pdf 

If you have any test document about his PAM4 FPGA, there will be very helpful for us to understand the question. 

Thank you so much!  Please feel free to let me know if you have any comments.

Best regards,

Lily

[Deshi_Intel · Accepted solution]

Hi,

PAM4 is new industry standard signal modulation technique, not something developed by Intel FPGA.

You can search in Internet to learn more about PAM4.

I found out below application note that explained on PAM4 that you can read further as well.

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an835.pdf

Thanks.

Regards,

dlim