Stream to Memory sgdma problem

[Altera_Forum]

I am having two problems with the sg-dma in my system. My first issue is that the sg-dma ready signal goes low after the first element of streaming data, then returns high on the third. This causes the second element to be skipped. I am streaming data at the same rate as the sg-dma clock. 

 My second issue is that I can not re-use the descriptors. I try to set the hardware owned bit to 1 by the following command: DMA_desc[0].control=128; The sg-dma ready signal goes high when I call the do_async_transfer() function, but it toggles low when it gets streaming data. No data is transferred to memory.  Can anyone help??  Thanks.

[Altera_Forum]

we also found another problem. RAM clock was 12ps out of phase.

[Altera_Forum]

Yes… I have been made my own dispacther and makes me cool. 

My dispatcher is nios less.  - Nios only do initialization at first.  - Nios get a ready address from dispatcher (like mutex way) - Dispatcher controls write master mSDGMA like round-robin (dual storage) TCP/IP troughput around 33Mbps 14 bit ADC x 1024 length @ 2kHz samples