ENV: stritix IV + altmemphy DDR3 controller.DDR write is sometimes unstable. I used signaltap to observe signals of local bus. I perform 2 experiments as the following. 1.When I stop writing DDR and read the same address. the value from DDR is stable. This proved that DDR read is stable 2.When I start writing DDR and read that address, the value are sometime unstable, serveral bits are wrong. any idea about the error ? thanks.
>You sure the hardware is OK?yes, I think hardware is OK. I use the following S4 Tai logic module. please google "S4 TAI Logic Module" I cannot post links right now. >All terminations are fine? Hardware terminations or pin setting ? >Is this happening, when tested on development kit ? Not on development kit, it's on my code. I used signaltap to observe signals of local bus. the signals satisfied the protocol.
current project use altmemphy.Is there any difference between altmemphy and uniphy ? 1. interface, and protocol ? 2. pin setting ? If it is not too diffcult to change, I may have chance to replace it.
It shouldn't be difficult. UniPHY is the new controller, which should replace ALTMEMPHY afaik. It will give You all the required information about the controller status if it's calibration is OK or not plus additional info.
Did you resolve your problem yet?Could you tell me how to resolve it? Ah, my skype ID is : hoai_viet_83 Please reply me as soon as possible. Thanks and best regards.