Suppress every third clock pulse

[Altera_Forum]

I have a need for a 150 MHz clock that has every third clock high period suppressed, looking as 101000101000 or 101100101100. Is it safe to use the basic 150MHz clock to drive a counter, decode an output and "AND" the clock with that signal, or do i get spikes etc. Any suggestions? I have a simple CPU design working on a DE1 board using verilog, and want to optimize the timing: short fetch cycle, longer the execute cycle.  

 Thanks   Nutson

[Altera_Forum]

Yes, having combinatorial logic act as a clock is prone to spikes. Go through a altclkctrl block(which you always go through to get onto a global) and then disable the clock. The design in the attached link does the same thing, although it's for a different reason(basically disabling every other clock to make a divided down clock): 

http://www.alteraforum.com/forum/showthread.php?t=1473&highlight=divide+clocks Good luck with timing analysis. Everything will be analyzed by the tighter setup requirements(which makes sense), so you would have to add a multicycle to the paths you want analyzed slower. (For the record, I'm still not sure what you're doing. Feeding logic with a clock like that will always have the logic run at the faster rate for a cycle, then at the slower rate for a cycle. So you still have to meet the faster timing. If you use an enable to disable some of the logic during the faster clock periods, then just do that and don't muck with the clock. My guess is that what you're trying to do could be accomplished better a different way, but again, I don't know the details...)

[Altera_Forum]

Thanks for the quick response. I will restate my problem; I have coded a simple non-pipelined CPU that uses only two states/instruction: fetch and execute. Now that I have it running at 100 MHz (50 MIPS, 10 nsec/state), I found the fetch cycle can be shortened to 5 nsec. Recoding the CPU for three states in an unpleasant option. I guess the best way is to start with a 200MHz clock, and write a simple 3 state machine that generates an asymetrical CPU clock, and feed this through the altclkctrl block. 

 Thanks   Nutson

[Altera_Forum]

You might also consider the option of using one clk plus (enable) signal to suppress the 3rd clock to the relevant part of your design

[Altera_Forum]

Kaz's suggestion is probably the best. It's not really recoding for three states, it's just disabling the slower registers for one clock cycle(and the logic would be pretty similar to what you're creating for the altclkctrl block, except it would be localized to your logic). Note that if you had the clock you asked for, your sysem would still need some correlation logic, as there's no way it knows the longer pulse is for the instruction and the shorter one for the fetch. On different power-ups you would have it occur differently each time. With a clock enable, you have direct control over it.

[Altera_Forum]

I will follow your suggestion. Practical: the main clocked component in my design, apart from several registers, is a dual port ram (altsyncram) of 512x32 bit. It has the option of a clock enable input. Would this signal do what I want, ignore one clock period on both a and b ports and maintain stable outputs from the previous clock?

[Altera_Forum]

Yep. When the clock enable is low, the RAM never sees the rising clock edge.

[Altera_Forum]

I have it working, thanks for the support. My CPU is running at 180 MHz now with 3 clocks / instruction. The clock enable is a good way of solving my timing optimization, it basically gives me a wait state, that I can use also in the future to wait for external memory and peripherals.  

 Nutson