Synthese failed on DSP-Builder "Out of Memory 4200MB"

[Altera_Forum]

Hallo  

 I'm a student of the univerity o Zurich (Switzerland) and I develop a mp3  encoder/decoder on a Dev Board DE2 Cyclone 2 with EP2C35F672 fpga.  The synthese on dsp-builder do not work, I became a errore message  "Out of memory 4200 MB".   My workstation have x64 OS Windows 7 Prof with 8GB RAM. Can I make settings in DSP-Builder for correct mapping with RAM?  Wath for features have the Quartus V9.1 with DSP-Builder V9.1? Does this Version 9.1 work better with RAM-mapping?    Thanks you.

[Altera_Forum]

it is actually pretty strange seeing out of memory targeting a CII device. i will take a look at your mdl.

[Altera_Forum]

i ran your model from the other thread. i changed clock_1.536MHz to clock_1536MHz, and unchecked the specify clock boxes in all of the blocks which used clock_1536MHz just to get it to compile. i was able to successfully run all the way through Signal Compiler's compile, though it did use a ton of RAM.

[Altera_Forum]

i am using MATLAB 2008b and Quartus II/DSP Builder 9.1

[Altera_Forum]

thank you for try a simulation on your pc. 

 I have changed my mdl-file, could you test this new file on your pc again? I became the same error "out of memory 4200GB", that's strange...   I use Matlab 2009b, quartus 9.0 and dsp-builder 9.0.   I have both quartus x32 and x64 on my pc, but is not the OS Win7 x64 that managed the mapping with RAM's?   Best regards...

[Altera_Forum]

I found the failure, I has insert a bus conversation on the output from my IIR with "signed int 16-bit in/out and make settings in DPRAM also signed int 32x16 bit and not inferred. 

The reason was, I has to large information with always inferred settings, but is not important at the output from my IIR, when the signal is 205.12584 or only 205. Now the consuption of my RAM are about 1200MB...   Thanks...

[Altera_Forum]

Hi, 

 I already "Out of memory 4200 MB". But this error is only when I use a parallel adder with 32 inputs.  I try to use 31 parallel adder with 2 inputs, but I receive the same error. I try also with Time set Altera Block with 48kHz and 50Mhz at the Output from the Adder.  Please could you analyse my circuit? Friday is the presentation...   Thanks.

[Altera_Forum]

in this circuit-version that I upload I try with 31 pipeline adder 2 inputs... the error is the same...

[Altera_Forum]

it looks like you go through a very wide demux through pipelined adders to a single output. can you change this to an accumulator that replaces the mux and the adder tree? this should save lots of resources and ease the memory constraints of your design.

[Altera_Forum]

how can I make a accumulator with dsp-builder blocks?

[Altera_Forum]

just like an accumulator looks. :) 

 a 2 input adder which feeds into a delay block. the first input of the adder is the same as your demux, and the 2nd comes from the output of the delay block. you can turn on the sclr function in your delay block to clear the accumulator every time you start a cycle. the sclr will be connected to one of the counters (or counter into a comparator) of your design. so clear whenever counter = 0 or 255 or whatever.

[Altera_Forum]

hi that's true ;) 

 I make the accumulator with only a adder and a delay block. I hope I make also how dou you explain.  Could you see in the mdl-file that is right so? But I bacame still the error "Out of memory 4200 MB"  I cannot do no more and on Friday am already the presentation :eek:  thanks any way...

[Altera_Forum]

here e part of the **** error-message: 

  *************************************************    for hierarchy "u4_audio_path_GN:auto_inst|u4_audio_path_GN_u4_audio_path_Filterbank:u4_audio_path_Filterbank_0|u4_audio_path_GN_u4_audio_path_Filterbank_IIR_Block:u4_audio_path_Filterbank_IIR_Block_0|alt_dspbuilder_cast_GNI6QQPJVL:cast37" Info: Elaborating entity "alt_dspbuilder_SBF" for hierarchy "u4_audio_path_GN:auto_inst|u4_audio_path_GN_u4_audio_path_Filterbank:u4_audio_path_Filterbank_0|u4_audio_path_GN_u4_audio_path_Filterbank_IIR_Block:u4_audio_path_Filterbank_IIR_Block_0|alt_dspbuilder_cast_GNI6QQPJVL:cast37|alt_dspbuilder_SBF:Outputi" Info: Elaborating entity "alt_dspbuilder_cast_GNIYDGYA4Y" for hierarchy "u4_audio_path_GN:auto_inst|u4_audio_path_GN_u4_audio_path_Filterbank:u4_audio_path_Filterbank_0|u4_audio_path_GN_u4_audio_path_Filterbank_IIR_Block:u4_audio_path_Filterbank_IIR_Block_0|alt_dspbuilder_cast_GNIYDGYA4Y:cast38" Info: Elaborating entity "alt_dspbuilder_SBF" for hierarchy "u4_audio_path_GN:auto_inst|u4_audio_path_GN_u4_audio_path_Filterbank:u4_audio_path_Filterbank_0|u4_audio_path_GN_u4_audio_path_Filterbank_IIR_Block:u4_audio_path_Filterbank_IIR_Block_0|alt_dspbuilder_cast_GNIYDGYA4Y:cast38|alt_dspbuilder_SBF:Outputi" Info: Elaborating entity "alt_dspbuilder_cast_GNQHDBGTKE" for hierarchy "u4_audio_path_GN:auto_inst|u4_audio_path_GN_u4_audio_path_Filterbank:u4_audio_path_Filterbank_0|u4_audio_path_GN_u4_audio_path_Filterbank_IIR_Block:u4_audio_path_Filterbank_IIR_Block_0|alt_dspbuilder_cast_GNQHDBGTKE:cast39" Info: Elaborating entity "alt_dspbuilder_SBF" for hierarchy "u4_audio_path_GN:auto_inst|u4_audio_path_GN_u4_audio_path_Filterbank:u4_audio_path_Filterbank_0|u4_audio_path_GN_u4_audio_path_Filterbank_IIR_Block:u4_audio_path_Filterbank_IIR_Block_0|alt_dspbuilder_cast_GNQHDBGTKE:cast39|alt_dspbuilder_SBF:Outputi" Info: Elaborating entity "alt_dspbuilder_cast_GNF5LN5WC3" for hierarchy "u4_audio_path_GN:auto_inst|u4_audio_path_GN_u4_audio_path_Filterbank:u4_audio_path_Filterbank_0|alt_dspbuilder_cast_GNF5LN5WC3:cast40" Info: Elaborating entity "alt_dspbuilder_SBF" for hierarchy "u4_audio_path_GN:auto_inst|u4_audio_path_GN_u4_audio_path_Filterbank:u4_audio_path_Filterbank_0|alt_dspbuilder_cast_GNF5LN5WC3:cast40|alt_dspbuilder_SBF:Outputi" Info: Elaborating entity "alt_dspbuilder_sAltrPropagate" for hierarchy "u4_audio_path_GN:auto_inst|u4_audio_path_GN_u4_audio_path_Filterbank:u4_audio_path_Filterbank_0|alt_dspbuilder_cast_GNF5LN5WC3:cast40|alt_dspbuilder_SBF:Outputi|alt_dspbuilder_sAltrPropagate:u0" Info: Elaborating entity "alt_dspbuilder_cast_GNEZIJ6WON" for hierarchy "u4_audio_path_GN:auto_inst|u4_audio_path_GN_u4_audio_path_Filterbank:u4_audio_path_Filterbank_0|alt_dspbuilder_cast_GNEZIJ6WON:cast41" Info: Elaborating entity "alt_dspbuilder_SBF" for hierarchy "u4_audio_path_GN:auto_inst|u4_audio_path_GN_u4_audio_path_Filterbank:u4_audio_path_Filterbank_0|alt_dspbuilder_cast_GNEZIJ6WON:cast41|alt_dspbuilder_SBF:Outputi" Info: Elaborating entity "alt_dspbuilder_sAltrPropagate" for hierarchy "u4_audio_path_GN:auto_inst|u4_audio_path_GN_u4_audio_path_Filterbank:u4_audio_path_Filterbank_0|alt_dspbuilder_cast_GNEZIJ6WON:cast41|alt_dspbuilder_SBF:Outputi|alt_dspbuilder_sAltrPropagate:u0" Info: Elaborating entity "alt_dspbuilder_cast_GNRB652TKN" for hierarchy "u4_audio_path_GN:auto_inst|u4_audio_path_GN_u4_audio_path_Filterbank:u4_audio_path_Filterbank_0|alt_dspbuilder_cast_GNRB652TKN:cast42" Info: Elaborating entity "alt_dspbuilder_SBF" for hierarchy "u4_audio_path_GN:auto_inst|u4_audio_path_GN_u4_audio_path_Filterbank:u4_audio_path_Filterbank_0|alt_dspbuilder_cast_GNRB652TKN:cast42|alt_dspbuilder_SBF:Outputi" Info: Elaborating entity "alt_dspbuilder_port_GNW7EMWS6I" for hierarchy "u4_audio_path_GN:auto_inst|alt_dspbuilder_port_GNW7EMWS6I:isv18_toggle_switch_0" Warning (10296): VHDL warning at alt_dspbuilder_port_GNW7EMWS6I.vhd(15): ignored assignment of value to null range Info: Elaborating entity "alt_dspbuilder_cast_GNRXPMS6SV" for hierarchy "u4_audio_path_GN:auto_inst|alt_dspbuilder_cast_GNRXPMS6SV:cast62" Info: Elaborating entity "alt_dspbuilder_SBF" for hierarchy "u4_audio_path_GN:auto_inst|alt_dspbuilder_cast_GNRXPMS6SV:cast62|alt_dspbuilder_SBF:Outputi" Info: Elaborating entity "alt_dspbuilder_sAltrPropagate" for hierarchy "u4_audio_path_GN:auto_inst|alt_dspbuilder_cast_GNRXPMS6SV:cast62|alt_dspbuilder_SBF:Outputi|alt_dspbuilder_sAltrPropagate:u0" Info: Elaborating entity "alt_dspbuilder_cast_GNLYHRR3W4" for hierarchy "u4_audio_path_GN:auto_inst|alt_dspbuilder_cast_GNLYHRR3W4:cast63" Info: Elaborating entity "alt_dspbuilder_SBF" for hierarchy "u4_audio_path_GN:auto_inst|alt_dspbuilder_cast_GNLYHRR3W4:cast63|alt_dspbuilder_SBF:Outputi" Info: Elaborating entity "alt_dspbuilder_sAltrPropagate" for hierarchy "u4_audio_path_GN:auto_inst|alt_dspbuilder_cast_GNLYHRR3W4:cast63|alt_dspbuilder_SBF:Outputi|alt_dspbuilder_sAltrPropagate:u0"   Out of memory in module quartus_map.exe (4253 megabytes used) Error: Error during compilation: Synthesis failed   ********************************************  maybe you reconize any thing...

[Altera_Forum]

i ran out of memory also with this model. this is strange, the model isn't so huge as to expect running out of RAM, especially on a CII device. next thing i can advise is to only to the actual DSP processing in DSP Builder and leave inputs for your coefficient loading which can be done in HDL or schematic capture in the actual Quartus project.

[Altera_Forum]

can you make this replacment, and try again or is this complicate? I d'ont now wath do you exactly means with 

 next thing i can advise is to only to the actual DSP processing in DSP Builder and leave inputs for your coefficient loading which can be done in HDL or schematic capture in the actual Quartus project.

[Altera_Forum]

Can you list the contents of the generated code directory? (Screenshot windows explorer or copy and paste the output of "dir") 

 I think this is the <mdlname>_dspbuilder/db directory.

[Altera_Forum]

the output of dir are to large for post it 87MB. 

Can you try to make a synthese on your workstation and see was the output created?  In the attachment you find the mdl-file with the Main_Coeff.mat (load Main_Coeff.mat in Matlab workspace)  Thanks...

[Altera_Forum]

I haven't got DSP Builder set up at the moment, so I was trying to get some preliminary information while I'm getting my machine set up. 

 If the list is too big then can you tell me whether there are .vhd files? Specifically ones that match *GN*.vhd?

[Altera_Forum]

here all *GN*.vhd files... 

 please tell me when you must have other .vhd-files...

[Altera_Forum]

ore better, here all .vhd-files incl. *GN*.vhd

[Altera_Forum]

Looking at the VHDL, I think the problem is that the bit widths in your design are huge. Looking at alt_dspbuilder_product_GNWK6HVYWC.vhd, you have a multiplier with inputs of size 9044 and output of size 18088 and with a pipeline length of 0. 

 Is that intended? Do you have that in the MDL file as well? (I'll try harder to get DSPB over here so I can stop asking questions soon)