Synthese failed on DSP-Builder "Out of Memory 4200MB"

[Altera_Forum]

Hallo  

 I'm a student of the univerity o Zurich (Switzerland) and I develop a mp3  encoder/decoder on a Dev Board DE2 Cyclone 2 with EP2C35F672 fpga.  The synthese on dsp-builder do not work, I became a errore message  "Out of memory 4200 MB".   My workstation have x64 OS Windows 7 Prof with 8GB RAM. Can I make settings in DSP-Builder for correct mapping with RAM?  Wath for features have the Quartus V9.1 with DSP-Builder V9.1? Does this Version 9.1 work better with RAM-mapping?    Thanks you.

[Altera_Forum]

I've now checked your MDL file and I can confirm that the MDL file has this problem as well. (To see the bit widths click the "Format" menu, follow "Port/Signal Displays" and select "Port Data Types". 

 Your IIR_Block subsystem has inputs of type SBF_1_18, which means 1 bit left of the binary point and 18 points to the right. Its output has type SBF_4436_4608, which you then reduce down to a 16 bit integer.  The problem mostly seems to stem from you using Inferred as the Bus Type. The inferral seems quite wrong. For Gain_1, you have INT_16 (bitwidth 16) X SBF_1_18 (bitwidth 19) = SBF_32_36 (bitwidth 68), when it should be SBF_17_18 (bitwidth 35).  As a short term fix I would try not using "Inferred", but manually inputting the width.

[Altera_Forum]

nice debugging, certainly explains why a CII design ran out of memory.