System console giving up when running the command "TEST_PHYSERIAL_LOOPBACK 0 1G 1000"

[Vamsi_21]

Hi,
I have generated the design example for Low latency ethernet 10g mac intel fpga ip-- 10M/100M/1G/10G example design(Arria 10) by following the below document.
https://www.intel.com/content/www/us/en/docs/programmable/683063/19-1-19-1/10m-100m-1g-10g-ethernet-design-example.html

While testing it on the hardware, I am getting the below error from system console.

“error: master_write_32: This transaction did not complete in 60 seconds. System console is giving up.
While executing
“master_write_32 sport_id $address $wdata”
(procedure “reg_write” line 7)
invoked from within
“reg_write $PHY_IP_BASE_ADDR $seq_control 0X111”
(procedure “SETPHY_SPEED_1G” line
invoked from within
“CONFIG_IPORT $speed_test”
(procedure “TEST_PHYSERIAL_LOOPBACK” line 10)
invoked from within
TEST_PHYSERIAL_LOOPBACK 0 1G 1000”

I have changed the USB blaster frequency to 16MHz,6MHz but still I am getting the issue.

Details:

Quartus used : Quartus prime 22.2
Board :Intel arria 10 GX development board
Device : 10AX115S2F45I1SG.

Below are the clock pin assignments
Name pin assigned
mm_clk 125Mhz BD24 clk_125
ref_clk_1g 125MHz N37 REFCLK_SMA (modified using clk controller).
ref_clk_10g 644.53125Mhz AA37 REFCLK_SFP

[ZiYing_Intel]

Hi Vamsi_21,

May I know that you are using your own board or devkit during the testing?

Best regards,

zying

[Vamsi_21]

Hi,
Iam using intel Arria10 GX development board for the testing.
Device:10AX115S2F45I1SG

[ZiYing_Intel]

Hi Vamsi_21,

I can run the design example successfully.

Best regards,

zying

[ZiYing_Intel]

Hi Vamsi_21,

Can you check how many jtag service ports and what index number of desired port by "get_service_paths master" command in the system console?

This index number is used in the "hwtest/basic/basic.tcl".

Best regards,

zying

[Vamsi_21]

Hi,

I have run the "get_service_paths master" command in the system console.
Below i am attaching the image of the system console window.
Previous screenshots which you have attached, i am not able to view or download them.

[ZiYing_Intel]

Hi Vamsi_21,

This index number is used in the "hwtest/basic/basic.tcl"

Best regards,

zying

[Vamsi_21]

Hi,
The same index number is there in the hwtesting/basic/basic.tcl.
Below iam attaching the screenshot.

[ZiYing_Intel]

Hi Vamsi,

I already sent the example design to your email and glad to hear that you can run successfully. For the issue on 100G, can you share your .qar file here?

Best regards,

zying

[Vamsi_21]

Hi, 
Can you the share the  .tcl scripts for 10G Etherent which you have used for testing on the board because for any test i run iam getting the same output irrespective of the channel, data-rate, burstsize .

[ZiYing_Intel]

Hi Vamsi,

Here's the .tcl script.

Best regards,

zying

[Vamsi_21]

Hi, 
I have tested on the board with the .tcl scripts you have shared and have found the irrespective of any changes like burst-size, data rate  and different tests like PHYSERIAL_LOOPBACK and SMA_LOOPBACK
It is showing same "throughput calculated" for every speed.
Below I am attaching the screenshots for:
PHYSERIAL_LOOPBACK for channel 0 , 1G speed, 1000 burst size,
PHYSERIAL_LOOPBACK for channel 0, 10G speed, 1000 burst size,
SMA_LOOPBAACK for channel 0, 10G speed, 1000 burst size.

device details:
NAME: ARRIA 10 GX development board
DEVICE: 10AX115S2F45I1SG

[ZiYing_Intel]

Hi Vamsi,

I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

Best regards,

zying

[Vamsi_21]

• Hello,
  
  Iam testing with the tcl scripts which you have shared and need some time analysing them because previously when i tested on the board i got the same results for every test irrespective of channel, data- rate , burst size

[Vamsi_21]

Hi,
As I have mentioned above , I have checked with the .tcl scripts you have shared and found the output was same irrespective of any test_speed , can you look into this issue?
@ZiYing_Intel 

[ZiYing_Intel]

Hi Vamsi,

Give me some time to work on this issue.

Best regards,

zying

[Vamsi_21]

Hi, 
Is there any update ?

[Vamsi_21]

Hi,
Is there any update from your side?

@ZiYing_Intel 

[ZiYing_Intel]

Hi Vamsi_21,

Currently I don't have any update. I now transition this thread to community support. The community users will continue to help you on this thread.

Best regards,

zying

[Vamsi_21]

Hi, 
Is there any hardware_test_design avaialble for Low latency 100g Ethernet intel FPGA ip example design.
I have generated an example design but it isn't working on the hardware ,  I am getting the below error:
"TTK failed reading from PHY slave_10000, cannot enable TTK functionality for this PHY. Please verify the reconfig_clk is running and ensure this PHY is not stuck in reset."

This error is same as the one i got for 10g ethernet design , so can you help me on this issue for the 100g design as well.

[ZiYing_Intel]

Hi Vamsi,

I sent the example design for 100g to your email dy. Hope it was helpful to you.

Best regards,

zying

[Vamsi_21]

Hi, 

Can you share the 100g design for 22.2 Quartus version.
While trying to open the design you sent it is showing " project archive restoration failed. project may be archived from a different quartus version."