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TSE gets the wrong local loopback and received data!

Honored Contributor II

The software I am using is quartus ll sp1 11.0. The device I am using is EP4CE15F17C8. TSE was configered shown as below: 


I just want to use the TSE to control a 100Mbits PHY. 

A simulation project was generated as soon as TSE generated by quartus ll sp1 11.0,from which I got the value of registers shown as below: 

parameter C_data_scratch = 32'haaaaaaaa; 

parameter C_data_command_config = 32'h04088033;  

parameter C_data_addr_mac_0 = 32'h22334450; 

parameter C_data_addr_mac_1 = 32'h0000ee11; 

parameter C_data_frm_length = 32'h000005ee; 

parameter C_data_pause_quant = 32'h0000000f;  

parameter C_data_rx_section_empty = 32'h00000000; 

parameter C_data_rx_section_full = 32'h00000010; 

parameter C_data_tx_section_empty = 32'h00000010; 

parameter C_data_tx_section_full = 32'h00000010; 

parameter C_data_rx_almost_empty = 32'h00000008; 

parameter C_data_rx_almost_full = 32'h00000008; 

parameter C_data_tx_almost_empty = 32'h00000008; 

parameter C_data_tx_almost_full = 32'h0000000a; 

parameter C_data_mdio_addr0 = 32'h00000001; 

parameter C_data_mdio_addr1 = 32'h00000001; 

parameter C_data_tx_ipg_length = 32'h0000000c; 


0x00,0x01,0x02,0x03,0x04,......,0x7A,0x7B,0x7C,0x7D,0x7E,0x7F these numbers were stored in the rom of fpga. Data was  

transmitted to PC by the protocol of UDP. I got one frame of data by a tool on PC,and the result shown as below: 


From the picture above, I could judge the data transmitted to PC was right. 



I got a frame of local loopback data by signaltap ll shown as below: 






The enlarged beginning of the frame of data shown as below: 



The enlarged end of the frame of data shown as below: 



From the pictures above, we could see the data transmitted to PC was 8C 89 A5 B8 EE 89 22 33 44 55 66 AA ...... 79 7A 7B 7C 7D 7E 7F  

but local loopback data changed to be 89 A5 B8 EE 89 22 33 44 55 66 AA ...... 79 7A 7B 7C 7D 7E 7F D0 


And when I turned off local loopback function,receiving data from PC,I got the same result too. But I found it to be right if I simulated my project by modelsim. 


Is anyone who familiar with TSE ipcore can help me?
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2 Replies
Honored Contributor II

It could be a timing problem. Is your design properly constrained and does it meet all timing requirements? Did you put any constraints on the i/o pins to the PHY?

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Honored Contributor II

I didn't put any constraints on the i/o pins to the PHY.But I watched the timing of MII interface(tx_clk,m_tx_d,m_tx_en,m_tx_err,rx_clk_0,m_rx_d,m_rx_en,m_rx_err,m_rx_col,m_rx_crs ). 

They were right.
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