FPGA Intellectual Property
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TSE with UDP without NIOS

Honored Contributor II



i'm currently working on an implementation of a triple-speed-ethernet core, with use of a 1 Gbit Ethernet Interface, i use the SGMII interface to a phy. I have implemented the design of the TSE in a greater vhdl project with some other things around. 

I have searched the entire forum, but couldn't get the right answers. 


Here my problem: 


The aim is to send 32Bit Data per frame via UDP from the PC to the FPGA i should work on a GBit Ethernet. The implementation of the TSE with the rest of the parts of the design was no problem and the simulation worked fine, but somehow i have to send the data to the board and currently i have no idea. 


My knowledge of network technology is based only on the use of sockets in c programming, well it would be great if it could work so easy but... 


I know that there is a solution in the use of a Nios with nichestack TCP/IP, but i was asked that i should not use one (to much other things in the fpga). My problem now is how can i implement a stack or socket or something like that to send udp-packets from my pc to the board, the other way is actually not important. 

Well i don't want the exact solutions but some help or links to some knowledge would be helpful. 

Maybe some other way to send data from the pc over the ethernet..., but a solution with sockets would by great. 


This all is part of my bachelor work, i have good knowledge in c programming, and the vhdl basics worked fine until know but this is quite something... 


I hope that someone could help me. 


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Honored Contributor II

Take a look at this page: http://www.alterawiki.com/wiki/nios_ii_udp_offload_example 


There are hardware blocks that implement UDP as well as a light weight flow control/checking scheme. It's not exactly what you are looking for but it should give you some ideas.
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