We have made a set of custom boards incorporating the Altera chip as documented in the information of the form. We have an issue directly related to the DDR2 controller on 2 of the 12 boards we have tested so far. What happens on the boards with issues is the DDR2 controller signal "afi_reset" is asserted periodically during operation. If this assertion happens at the wrong time it will create errors. We are wondering what is the cause of this "afi_reset" assertion and what can we do on our end to make sure it doesn't happen? I am guessing it has to do with PCB variability given that it only happens on a small percent of boards.
FPGA device used is Cyclone V GT.
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The afi_reset signal will assert based on 2 conditions:
- PHY is reset
- PLL loses lock : This indicate that your afi_clk is not stable yet thus it will assert the reset signal until the PLL is locked.
For more details, you can refer to this user guide : https://www.intel.com/content/dam/altera-www/global/ja_JP/pdfs/literature/hb/external-memory/emi_ddr3up_ug.pdf
Hope this helps
Thank you for getting back to me. Do you know what can cause a reset to the PHY? Also do you know why the PLL might lose lock? I have two circuit boards, with the exact same hardware and Altera firmware but this issue only happens with one of them. Does anything come to mind?
The reset pin is introduced for system stability. This Reset pin is an active-low signal and the main cause this reset pin asserted is due to the PLL lose lock.
And the PLL might lose lock due to a number of possible causes. As far as I know, two main reasons of that kind of behavioral is clock source quality and temperature in which device is working. I would suggest going through below check-list that may help.
Hopefully this is helpful . 😊