Hi folks,I'm trying to think of a solution to make time-based simulation IP (verilog). We use vencrypt to protect the ip already. I was thinking about the possibility of using system calls as such: 1) Write build date into encrypted hdl During compilation/simulation: 2) System call to get os -> branch for next step 3) System call to write date into a file 4) Use system task to read file 5) In encrypted logic, compare current date vs build date and kill if its over X days 6) System call to delete file Obviously not a great solution and easily defeated if you were to figure out what it was doing. Any other suggestions would be appreciated.
--- Quote Start --- I'm trying to think of a solution to make time-based simulation IP (verilog). We use vencrypt to protect the ip already. --- Quote End --- A counter? Eg., 1hr at 100MHz = 38-bits counter. Load and enable the counter on configuration, and then 'stop' working when it hits zero. This can of course be defeated by reconfiguring the device every hour ... but so can the time on an OS. Cheers, Dave
--- Quote Start --- We do something like that in synth already. My hope was for a simulation solution --- Quote End --- Use an assertion based on the counter? But of course an hour of real time is an infinity in simulation time :) Are PLI calls supported in the simulators you expect to use? Perhaps you could do what you want that way, but at least its hidden inside your source. Why PLI? Well, you if you're going to make OS calls, I think that is your only option. Cheers, Dave
Heh. We can timebomb the sim after a certain point sure, but up until that point the IP will work perfectly. And all it takes is rerunning the sim. I've tested $system calls on Modelsim SE and it's supported, but I can't say about the other flavors and simulators. Perhaps since Altera seems to be going the systemverilog route in the V family, there might be an SV solution for future dev.
--- Quote Start --- I've tested $system calls on Modelsim SE and it's supported, but I can't say about the other flavors and simulators. --- Quote End --- The SystemVerilog spec defines system on page 542, Section 20.18.1. --- Quote Start --- $system makes a call to the C function system(). The C function executes the argument passed to it as if the argument was executed from the terminal. $system can be called as either a task or a function. When called as a function, it returns the return value of the call to system() with data type int. If $system is called with no string argument, the C function system() will be called with the NULL string. The example below calls $system as a task to rename a file. module top; initial $system("mv design.v adder.v"); endmodule --- Quote End --- Looks like you've got a way of getting the time without writing any extra code or using PLI. Since this is part of the spec, other simulators should implement it. For Quartus, just put a synthesis directive around the $system call, and implement your hardware counter kill logic instead. Cheers, Dave