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Timing constraint with DDR2 UniPHY IP


Project: NIOS + DDR2 UniPHY + other defined module by me.

After I set clock in SDC file, I find all inputs and outputs constraint are done.

In fact, I did not inputs and outputs.

It seems automatic generated by UniPHY SDC file covered inputs and outputs.


1) I think UniPHY IP SDC file only covers I/O related to memeory, why it impacts other I/O ? such as some ADC, spi bus, emmc interface....

2) I need to define timing constraint condition in my project SDC for other I/O, will it be ignored by Quartus due to exist UniPHY IP SDC?



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