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XShen1
Novice
67 Views

Why this signal of ALTPLL is a base clk?

Why this signal of ALTPLL is a base clk?

IP: ALPLL

Quartua Prime 18.0 timing analyzer.

1.JPG

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2 Replies
KennyT_Intel
Moderator
42 Views

This happened usually you did not use the derive_PLL_clocks in your sdc files. Can you check your *.sdc?

XShen1
Novice
42 Views

You are right. Thanks!

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