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6153 Discussions

Why this signal of ALTPLL is a base clk?

XQSHEN
Novice
‎06-16-2020 01:44 PM
140 Views

Why this signal of ALTPLL is a base clk?

IP: ALPLL

Quartua Prime 18.0 timing analyzer.

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Kenny_Tan
Moderator
‎06-17-2020 02:46 AM
115 Views

This happened usually you did not use the derive_PLL_clocks in your sdc files. Can you check your *.sdc?

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XQSHEN
Novice
‎06-17-2020 12:26 PM
115 Views

You are right. Thanks!

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For more complete information about compiler optimizations, see our Optimization Notice.