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很抱歉，您必须验证才能完成此操作。请单击您电子邮件中的验证链接。您可以重新发送，通过 配置文件.
Why this signal of ALTPLL is a base clk?
IP: ALPLL
Quartua Prime 18.0 timing analyzer.
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This happened usually you did not use the derive_PLL_clocks in your sdc files. Can you check your *.sdc?
You are right. Thanks!
