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PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Transceiver PHY IP Core for CPRI Slave Mode

Honored Contributor II



I am going to construct CPRI PHY by using the transceiver PHY IP Core from Altera. When I investigate the clock structure of the system, I take the CPRI IP Core from Altera as my reference. 


My question is, if I need to support CPRI Slave mode, it seems that I can only choose Native PHY IP Core because only it can separately expose the cdr_ref_clk, i.e. RX CDR reference clock, to the developer. Other transceiver PHY IP Core all connect the RX CDR reference clock to the TX CMU reference clock.  


Is there any method to use other transceiver PHY IP Cores for CPRI Slave mode, for instance, Deterministic Latency PHY IP Core or Custom PHY IP Core? 


Best regards, 

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