Apparently the 16550 UART core wasn't supposed to appear as a supported IP component:http://www.altera.com/support/kdb/solutions/rd09172013_912.html Altera does has a non-16550 UART (no FIFO) available in qsys, docs available in the embedded IP user's guide: http://www.altera.com/literature/ug/ug_embedded_ip.pdf There is also a "FIFOed Avalon UART" on the wiki: http://www.alterawiki.com/wiki/fifoed_avalon_uart
I am trying to sort out the same UART issue. The UART16550 might be the purchased 3rd party core. I placed in in Qsys 13.0sp1 Arriaii and I was not able to compile. I am trying to use the standard UART and DMA and Memory to make version now. Also the FIFOed Avalon UART seem to be a SOPC version that does not show up in 12.0 and I do not know how to make this code with in Qsys.PS. There is a Hard Core UART http://www.altera.com/devices/fpga/cyclone-v-fpgas/hard-processor-system/cyv-soc-hps.html.