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Honored Contributor I
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Transciver phy IP Core problem

https://alteraforum.com/forum/attachment.php?attachmentid=14161&stc=1 Hii  

 

In my projet I am using Cylone V GX and I work with Phy nativ transciver for transmit a data at speed 1Gbit on fabric with sfp. 

 

I use with 100MHz local clock and REFCLK 100MHz differential clock (LVDS) 

 

The transciver work and flag of sync_status is '1' but all 4 secoand my flag that seen if data recieve ok ("data_ok") look that the data received wrrong and it is happend when "ctrl detect" not received and I does not know why it is happend if someone can halp me? (Seen picture of signal tap)
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