I am using Qsys Pro 17.0.0 for Arria 10.
My Qsys system instantiates a DDR4 EMIF, which is the AVMM slave, and four custom logic blocks which are the masters. Masters and slave do not run at the same frequency : 125 MHz for the AVMM masters, and 200 MHz for the slave (EMIF).
In order to optimize the performances, I tried to use the bursts for the read requests, with a maximum of 64 words. A AVMM pipeline bridge working at 125MHz is instantiated to factorize the clock crossing 125MHz <-> 200MHz.
I have attached a screenshot of this Qsys system.
The read transfers work but are not efficient. Indeed, according to Signal Tap, in response to a read request with a burstcount between 2 and 64, the readdatavalid signal at the EMIF’s output is a continuous 1 (1 word per clock cycle). However the readdatavalid signals at the masters’ input are discontinuous (1 word every 2 clock cycles). The arbiters or the clock crossing adapters between the slave and the masters must reduce the transfer efficiency. Despite this, the expected number of words is exchanged.
Do anyone know a way to optimize the transfer efficiency?