FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5950 Discussions

Seriallite II simulation no EOP

OShul
Beginner
1,269 Views

I have set up a design containing a Seriallite II core with TSIZE=4 => 32 bits.

The core is Transmit and receive combined, with datarate of 3125 MBps, with only packets enabled. the core is generated using Quartus 18.1 standard

In my testbench i have placed a 2nd copy of my design as the receiver.

The simulation shows rr_link between the 2 IPs is ok.

When i send a data packet from my design, on the receiving end i see the SOP signal and the dataval signals, as well as the data bus are ok, but no EOP signal.

Please advise.

Thanks,

Oded

0 Kudos
2 Replies
AnandRaj_S_Intel
Employee
98 Views

Hi,

 

Test-bench which you have written is almost same as auto generated test-bench.

So refer the auto generated test-bench and crosscheck.

Can Attached the Project & test-bench.

 

Regards

Anand

OShul
Beginner
98 Views

Hi anand,

Thanks for replying

 

For Arria V devices, such as mine The auto generated testbench produced by Quartus 18.1 does does not compile :

"The Configure Transceiver page is disabled when you select Arria V, Cyclone V, or Stratix V as the target device family. To add a transceiver, you are required to instantiate the Custom PHY IP core."

 

I hope the way i connected them is ok, since there is no real reference for this (only applicable example is stratix iv on quartus 12, which has totally different pins).

 

Because of this, the generated test-bench is correct the same way my design is correct 😥

 

I will try to attach my the relevant files.

 

Regards

Oded

Reply