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Cannot simulate array of Fifos

DNguy4
Beginner
945 Views

Hi,

I use an array of Intel fifo_x16 in my design and i cannot simulate it. The outputs of the fifo (data out, used words, empty, full) are always undefined even though all the inputs are valid. To debug this issue, i try the following:

  • Create simple design and instantiate one fifo in this design, and everything works fine. I can easily simulate the fifo in this design.
  • Create another simple design and instantiate an array of 3 fifos, and i cannot simulate it. The outputs of these fifos are always undefined. even though all the inputs are valid. This is teh same problem as my original problem. Is there anything special I need to do when instantiate an array of fifo? Appreciate any feedback. Below is the simple vhdl design with the array of fifo. I use ModelSim DE-64 10.6e for simulation.

Thanks

 

library ieee;

use ieee.std_logic_1164.all ;

use ieee.numeric_std.all;

 

 

ENTITY TEST is

port ( clk : in std_logic;

reset : in std_logic;

pixels_in     : in std_logic_vector (0 to 47);

pixels_out : out std_logic_vector (0 to 47);

test_read : in std_logic;

test_write : in std_logic;

aclear : in  std_logic;

sclear : in std_logic;

full : out std_logic_vector(2 downto 0);

empty : out std_logic_vector(2 downto 0)

);

END;

ARCHITECTURE rtl of TEST is

 

 

type VID_FIFO is record

data_in : unsigned(15 downto 0);

write : std_logic;

read : std_logic;

clear_async : std_logic; 

clock : std_logic;  

clear_sync : std_logic;

data_out : std_logic_vector (15 downto 0);

num_words : std_logic_vector (9 downto 0);

full : std_logic ;

empty : std_logic;

end record;

type VID_FIFO_ARRAY is array (natural range <>) of VID_FIFO;

signal vid_fifos : VID_FIFO_ARRAY(0 to 2);

BEGIN

 

G1: for i in 0 to 2 generate

 

 VIDEO_BUFFER: entity work.Fifo_x16_fifo_181_cdbx3jq port map (

data => std_logic_vector(vid_fifos(i).data_in), 

wrreq => vid_fifos(i).write,

rdreq => vid_fifos(i).read,

clock => vid_fifos(i).clock,

aclr => vid_fifos(i).clear_async,

sclr => vid_fifos(i).clear_sync,

q => vid_fifos(i).data_out,

usedw => vid_fifos(i).num_words,

full => vid_fifos(i).full,

empty  => vid_fifos(i).empty

);

end generate;

 

VIDEO: PROCESS (ALL) -- at least the clock changes, so this process should be evaluate every clock

Begin

for i in 0 to 2 loop  

vid_fifos(i).write <= test_write;

vid_fifos(i).read <= test_read;

vid_fifos(i).clock <= clk;

vid_fifos(i).clear_async <= aclear;

vid_fifos(i).clear_sync <= sclear;

vid_fifos(i).data_in <= unsigned(pixels_in(i*16 to i*16 + 15));

pixels_out(i*16 to i*16 + 15) <= std_logic_vector(vid_fifos(i).data_out);

full(i) <= vid_fifos(i).full;

empty(i) <= vid_fifos(i).empty;

end loop;

END PROCESS VIDEO;

 

END ARCHITECTURE;

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1 Reply
DNguy4
Beginner
79 Views

I figure it is better if I attached the VHDL file instead of pasting it to the question. See attached.

Reply