Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,430 Views

Transmitting frames with Triple-Speed Ethernet MegaCore over Ethernet/RGMII

Hello, 

 

I'm working with Quartus II, and had implemented the Triple-Speed Ethernet Megacore. 

I simulate my design with ModelSim Altera Starter Edition. 

My hardware is the BeMicro CV A9 with a Cyclone V FPGA and a Micrel Phy (KSZ9021RN). 

 

I set the signals ff_tx_data, ff_tx_sop, ff_tx_eop and ff_tx_wren (from my PaketGenerator). And in my simulation, I got some signals on rgmii_out and tx_control (tx_control seems to be strange, isn't it?) Of course there is a 100-MHz-signal for ff_tx_clk and a 25-MHz-signal for tx_clk (I want to transmit at 100 MBit/s). 

 

Is the simulation right? 

 

And why my FPGA board doesn't work in reality and doesn't transmit any frames? (in the statistic counters of the TSE I got sometimes in register 0x1A one paket (but on my host I don't receive any paket), mostly I got in register 0x23 one paket - I send 10000 pakets in reallity and 10 pakets in simulation) 

 

Look also at the photos I added to this request. 

 

Kind regards, Matthias
0 Kudos
8 Replies
Altera_Forum
Honored Contributor I
46 Views

You must ensure that both the TSE and the PHY are in 100 MBit/s mode. There is a register to set in the TSE (and/or an external signal, depending on your project) to force the 100 MBit/s mode, and also some MDIO registers to set in the PHY chip to prevent Gigabit/s autonegotiation. Check the datasheet. I'm not familiar with that PHY or that board, but in addition you may have to switch to an MII interface instead of RGMII.

Altera_Forum
Honored Contributor I
46 Views

I think this isn't the problem. 

 

I set up my network card to full duplex, 100 MBit/s, no autonegotiation. 

I set up the phy to full duplex, 100 MBit/s, no autonegotiation (and it's also telling me, that it's working with these parameters). 

And I wrote 0x01000053 to the TSE register 0x2, so it has to be configured in full duplex, 10 MBit/s and 1000 MBit/s are disabled, no autonegotiation, no loop, tx and rx path enabled. 

 

On a test point on my pcb I measured 25 MHz at enet_gtx_clk (that is tx_clk from TSE). 

The phy rgmii interface is compliant to RGMII version 1.3. 

 

What about simulation? Do you think, I have forgotten any signals (to TSE)? 

Why tx_control is set up to '1' even the RGMII_out is just "0000"? And why tx_control stays at '1' till I reset my hole system?
Altera_Forum
Honored Contributor I
46 Views

A common mistake is to disable negotiation, not auto-negotiation. You need to have negotiation enabled, but disable gigabit speed if your cable doesn't support it. I've been there done that.

Altera_Forum
Honored Contributor I
46 Views

Your snapshots are impossible to read, probably because the forum automatically reduced the image size. Try and put them in a .zip file or use the png format, which IIRC isn't modified by the forum software. 

 

From what you are saying I assume that you are not using a CPU with the standard Altera driver? I seem to remember that the TSE behaves a lot better if a proper SW reset is done before using it. You can have a look at the Altera software driver, see how they do it and reproduce it in your project. IIRC this reset procedure takes a bunch of clock cycles so you must be sure to wait for it to be finished before doing anything else. The TSE also needs all its clocks (both on the Avalon Stream side and the [RG]MII side) for the reset procedure to complete correctly.
Altera_Forum
Honored Contributor I
46 Views

Here is the zip file with the three pictures.

Altera_Forum
Honored Contributor I
46 Views

@Galfonz: 

I just find some informations about auto-negotiation in documentation of TSE and phy, not about negotiation. What is the negotiation good for, if I fix speed to 100 MBit/s and full duplex on all devices? 

 

@ Daixiwen: 

CPU? There is no cpu or nios in my system. I parameterised the TSE by MegaWizard. 

The ports of my TSE are connected to following clocks: 

clk -> 50 MHz 

tx_clk -> 25 MHz (@ 100 MBit/s) 

rx_clk -> connected to the phy rx clock, has to be 25 MHz @ 100 MBit/s 

ff_rx_clk/ff_tx_clk -> I tried with 50 MHz and with 100 MHz, both without satisfying results. 

 

I assume TSE isn't working proper, too. But when I test my implementation I make a hardware reset, configure all my registers, make a software reset of TSE - and my system still isn't working correctly. Just one paket is (of 10000) transmitted correctly. Other pakets aren't transmitted. 

Here TSE Statistic Counters: 

Adresse 0x21A, Wert 0x0 

Adresse 0x61A, Wert 0x1 

Adresse 0x21B, Wert 0x0 

Adresse 0x61B, Wert 0x0 

Adresse 0x21C, Wert 0x0 

Adresse 0x61C, Wert 0x0 

Adresse 0x21D, Wert 0x0 

Adresse 0x61D, Wert 0x0 

Adresse 0x21E, Wert 0x0 

Adresse 0x61E, Wert 0x1F5E 

Adresse 0x21F, Wert 0x0 

Adresse 0x61F, Wert 0x0 

Adresse 0x220, Wert 0x0 

Adresse 0x620, Wert 0x0 

Adresse 0x221, Wert 0x0 

Adresse 0x621, Wert 0x0 

Adresse 0x222, Wert 0x0 

Adresse 0x622, Wert 0x0 

Adresse 0x223, Wert 0x0 

Adresse 0x623, Wert 0x1 

Adresse 0x224, Wert 0x0 

Adresse 0x624, Wert 0x0 

Adresse 0x225, Wert 0x0 

Adresse 0x625, Wert 0x0 

Adresse 0x226, Wert 0x0 

Adresse 0x626, Wert 0x0 

Adresse 0x227, Wert 0x0 

Adresse 0x627, Wert 0x0 

Adresse 0x228, Wert 0x0 

Adresse 0x628, Wert 0x2 

Adresse 0x229, Wert 0x0 

Adresse 0x629, Wert 0x0 

Adresse 0x22A, Wert 0x0 

Adresse 0x62A, Wert 0x0 

Adresse 0x22B, Wert 0x0 

Adresse 0x62B, Wert 0x0 

Adresse 0x22C, Wert 0x0 

Adresse 0x62C, Wert 0x0 

Adresse 0x22D, Wert 0x0 

Adresse 0x62D, Wert 0x0 

Adresse 0x22E, Wert 0x0 

Adresse 0x62E, Wert 0x0 

Adresse 0x22F, Wert 0x0 

Adresse 0x62F, Wert 0x0 

Adresse 0x230, Wert 0x0 

Adresse 0x630, Wert 0x0 

Adresse 0x231, Wert 0x0 

Adresse 0x631, Wert 0x0 

Adresse 0x232, Wert 0x0 

Adresse 0x632, Wert 0x0 

Adresse 0x233, Wert 0x0 

Adresse 0x633, Wert 0x0 

Adresse 0x234, Wert 0x0 

Adresse 0x634, Wert 0x0 

Adresse 0x235, Wert 0x0 

Adresse 0x635, Wert 0x0 

Adresse 0x236, Wert 0x0 

Adresse 0x636, Wert 0x0 

Adresse 0x237, Wert 0x0 

Adresse 0x637, Wert 0x0 

Adresse 0x238, Wert 0x0 

Adresse 0x638, Wert 0x0 

 

0x2.. - bits 31 to 16, 0x6.. - bits 15 to 0 

so 0x21A 0x61A -> 0x00000001 is TSE register 0x1A - aFramesTransmittedOK 

 

My generated pakets should have a size of 248 bytes - why register 0x1E is 0x1F5E? This are 8030 bytes! Too much! But why? 

 

 

(IIRC - If I remember correctly ?)
Altera_Forum
Honored Contributor I
46 Views

Yes IIRC means If I remember correctly, sorry ;) 

From what I am seeing from your wave files you are sending the packets correctly. The strange thing is that tx_control stays asserted even after the packet seems to be completely transmitted. The only odd thing that I can find out is that you have no clock on rx_clk. I know from experience that the TSE needs its clocks from the [R][G]MII side in order to complete its software reset cycle correctly. It could be that it isn't completely reset because of the lack of rx_clk. 

 

As for your real circuit, it could be a good idea to use signaltap on the signals in and out of the TSE and check that everything is the same than in the simulation. (and remember, if you monitor tx_clk and rx_clk in signaltap, you need a sampling frequency that is at least double that of the signals you monitor).
Altera_Forum
Honored Contributor I
46 Views

Negotiation must be enabled so that your system communicates with the other end of the link and the normal link startup negotiations can be done. Much more than just speed is agreed to between the ends. See the Ethernet spec if you are curious. If negotiation is disabled this communication cannot happen. So, disable gigabit but not negotiation. Check the LEDs on each end of the link to see if link is established.

Reply