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Triple Rate SDI Simulation Issues (VHDL)

Altera_Forum
Honored Contributor II
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Has anyone successfully simulated the triple rate SDI megacore function in VHDL? I know there are examples in verilog but some of us are required to use VHDL and cannot justify the premium for mixed language licenses for ModelSim. 

 

I've a working design in hardware, but when I attempt to simulate it using a separate transmitter looped back to a receiver, the receiver never comes back out of reset after dynamic reconfiguration as indicated by the rx_status bits (0x03) and the rx_clk goes high indefinitely.
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