This disagreement is present in user guides versions, 14.0, 15.0, 15.1 as figures 9.1 and table 9.1. In versions 16.0, 16.1 and 17.1 it is listed as figures 8.1 and table 8.1 as in the question.
Thanks for your patience & cooperation.
I checked it internally & it`s typo in Figure & it`s description & the correct frequency is 100 MHz as mentioned in table.
Thanks to pointing out it to us, it will update while document upgradation.
In addition, the input clock frequency for ff_tx_clk and ff_rx_clk signals to meet 1G bandwidth & it depends on width of FIFO that used while configuration. If width of the FIFO is 32-bit then these signal should have input clock at least 100 MHz & if it is 8-bit , then it needs to be at least 125 MHz.