Triple Speed Ethernet and Streaming at 1Gbps

[Altera_Forum]

Hi all, 

 I have a DE2-115 dev kit and I am looking into the feasibility of streaming data out the Gigabit port at 150Mbps. Here is where I am so far:  I got the webserver NIOS project working and can communicate to the board via a PC. Next, I stripped down the project and wrote a simple loop that streams UDP packets with an incrementing counter in its payload. This data goes inbound to a PC and I verified the arrival of the packets via Wireshark.  Now I am at the point where I need to implement my real design. The actual data I need to send at 150Mbps resides in the FPGA. The first thought I had is to get this data to the NIOS and use the sendto() command so that the stack takes care of inserting headers and eventually sending this packet to the TSE Mac. However, before I even start this approach my gut feeling tells me this won't reach the throughput I need since the NIOS is going to be the bottleneck.  It seems to me that the solution is to interface to the TSE directly. It looks like I will need my own hardware code that attaches the ethernet and IP headers along with my payload data and send it to the TSE if I am to achieve speeds of 150Mbps or more.  Am I headed in the right direction here? My concern is that I don't want to re-invent something if a solution to do what I want already exists. Just making sure I don't jump into the deep end if it is not necessary.

[Altera_Forum]

Yes you are right, 150Mbps using software on the Nios will be tricky to acheive, especially if the CPU also needs to do something else, like collect the data it needs to transmit. 

You can have a look at the udp offload example (http://www.alterawiki.com/wiki/nios_ii_udp_offload_example) on the Altera Wiki for an example of how you could do this in hardware.

[Altera_Forum]

I will start working on a very similar 1Gbps Ethernet streaming application soon and did some research already. A possible solution would be to offload UDP packet generation from the software strack to a packet generator hardware block you implement in FPGA logic. I was going to post the same Altera Wiki link, but it seems someone else was faster.  

 Should you find additional ressources or hints I would be happy if you could post them here!

[Altera_Forum]

Daixiwen, yes. The mere fact that the processor isn't only going to be sending data to the TSE, but also it would need to break up the data I want to send and encapsulate each payload calls for much more processing power than the NIOS has. A bit unfortunate because if the packets could be prepared in the NIOS then the design would be trivial. :) 

 Thank you for the link. It looks like others before me have come up with similar solutions which is reassuring.  I will have to get down into the trenches and try it out on my board before I can comment further. I will get back to you all with what I learn should anything interesting come up.