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Triple-speed Ethernet MAC reset

Altera_Forum
Honored Contributor II
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Hi, 

 

Sometimes after power-up, I noticed that the TSE MAC "ff_tx_rdy" output is low. So I added a manual reset of the MAC (reset input) and it fixed the issue. I found the following link where it recommends to reset the MAC once the "tbi_rx_clk" clock starts toggling : 

 

http://www.altera.com/support/kdb/solutions/rd07072009_137.html?gsa_pos=1&wt.oss_r=1&wt.oss=mac%20re... (http://www.altera.com/support/kdb/solutions/rd07072009_137.html?gsa_pos=1&wt.oss_r=1&wt.oss=mac%20re...

 

Which is what I've done. More than that, I did the same for the "tbi_tx_clk" clock domain, and I've OR'ed both resets to drive the MAC reset input. 

 

I also found that reset must be released once all the MAC clocks are stable (which is my case) : 

 

http://www.altera.com/support/kdb/solutions/rd11052009_719.html?gsa_pos=4&wt.oss_r=1&wt.oss=tse%20re... (http://www.altera.com/support/kdb/solutions/rd11052009_719.html?gsa_pos=4&wt.oss_r=1&wt.oss=tse%20re...

 

I have 2 MAC's in my design, and so far, only MAC# 2 has the issue. 

 

Any idea ? 

 

Martin
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