FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6424 Discussions

UART Core IP (RS-232 Serial Port)

dtopou1
Beginner
2,742 Views

I am having issue with UART (RS-232 Serial Port) Intel FPGA IP v19.2.0 generation on Quartus pro 22.4.

The the RX path dose not receive any data.  Generated code for the core seams wrong in module "dproc_qsys_uart_0_altera_avalon_uart_1920_tpslhhy_rx_stimulus_source" see attached generated code.  Replacing UART Core IP with Uart LW IP solves the problem so I will rule out wrong connections on my part.

 

0 Kudos
13 Replies
mabdrahi
Employee
2,692 Views

Hi,


I will comeback to you soon


0 Kudos
mabdrahi
Employee
2,664 Views

Hi,


What device are you using now?


0 Kudos
dtopou1
Beginner
2,648 Views
0 Kudos
mabdrahi
Employee
2,608 Views

Hi,


It seem i cant to reproduce the error.


may i know do you using GHRD or nit on your project and can you share the link?


0 Kudos
mabdrahi
Employee
2,591 Views

hi any update?


0 Kudos
dtopou1
Beginner
2,576 Views

Here is a new test project that has noting but the qsys with uart IP.  take a look at the RX signal and how it is been processed by the model.

0 Kudos
mabdrahi
Employee
2,490 Views

Hi,


After i open your design, I need to create my own top file right?, Because its does not here


0 Kudos
mabdrahi
Employee
2,481 Views

Hi,


I open your design and i saw error while opening the top file.


I would like to have a call with you to look more deeper


may i know when do you free?


what is your GMT, my GMT is +8.



0 Kudos
dtopou1
Beginner
2,468 Views

The example project is there to allow you to generate IP source code.  The only think you need to do is to generate qsys.  Then you can analyze the source code that it generated.

0 Kudos
mabdrahi
Employee
2,451 Views

Hi,


Yes, we can generate the uart from qsys.

I would like to suggest to you, using the GHRD(https://github.com/altera-opensource/ghrd-socfpga

) then generate the uart instantiate IP, porting over to top level. im not sure if you doing that already for your project.


0 Kudos
dtopou1
Beginner
2,415 Views

Is generated code resembles the code that I have attached?  If so can you take a look at the data RX path and in specific module "dproc_qsys_uart_0_altera_avalon_uart_1920_tpslhhy_rx_stimulus_source" and how we can remove "SIMULATION-ONLY CONTECTS" sections and replace it with the synthesis translation?  I really do not want simulation only contents I need to simulate normal UART RX behavior!

0 Kudos
mabdrahi
Employee
1,790 Views

Hi,


Apologies for being late as im try to debug your case and attending other case.

We using GSRD and modify it. By using this method it should nearly accomplish the customer project.

The code generated maybe difference from what you provide.


0 Kudos
mabdrahi
Employee
1,669 Views

Hi,


As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support


0 Kudos
Reply