I am trying to generate the example design for Serial Lite 3 streaming Intel Arria 10 FPGA IP after configuring the parameters and the preset. The process of generating the example design is taking more than 30 mins. I suspect there is something wrong or maybe I am missing some things.
I am trying to generate the design on Debian and I am using Quartus 18.1. I have also tested the generation on Windows and it sadly didn't generate.
I will happy to know if there are any pointers on how to solve this issue or to raise a service request.
Please find attached a screenshot of the process for your reference.
I have checked with Quartus Prime Pro 18.1. The Example design can be generated if you follow the following steps:
1. Select Preset "Standard Clocking Mode 6 x12.5G" and click "Apply". The Preset is located in window at bottom right of the Serial Lite III Streaming Intel Arria 10 FPGA IP.
2. Change Direction from "Duplex" to "Source".
You will not observe only 2 warning instead of 8 warnings as shown in your attached snapshot.