Unable to simulate DDR3 controller

[JuanEscobedo]

Hello,

I have a design with DDR3 and I am using the Altera  DDR3 SDRAM Controller with UniPHY for Intel FPGA IP to interface with it and I want to run a simulation that involves the controller and the actual DDR3 memory model. I have never had to run a simulation involving an external DDR memory so I want to start by running a simulation of the example design for the IP.

When configuring the IP, at the end, I enable the "Generate Example Design" and I see the respective folders _sim and _example_design created. This completes without errors.

Inside the _example_design folder, there are two additional ones: example_project and simulation. Inside the exaple_project folder, I see a QPF file. I can open that from Quartus as "Open Project".

However, after clicking "Analysis and Synthesis" and double clicking on the top level module, I get this error:

Trying to run Tools-> RTL Simulation doesn't give any errors but Questa never launches.

I am using Quartus 23.1 on a Windows 11 machine. 

Any help would be appreciated.

Juan Escobedo, Ph.D.

[AdzimZM_Intel]

Hi Juan Escobedo,

I believe the generated example design doesn't generate .qsys file and .ip file but it's generated the modules in .v or .sv or .vhdl.

Therefore, when you are clicking on top level file, it will show invalid Platform Designer file because no .qsys file is available.

You can goto the file by right click --> locate node --> locate in design file.

If you want to run the simulation, you can follow these steps:

1. Open the Questasim simulator.
2. Change the directory to *_example_design\simulation\<verilog or vhdl>\mentor
3. run command "do run.do" in Questa command prompt.

Link for reference: https://www.intel.com/content/www/us/en/docs/programmable/683385/17-0/simulating-the-example-design.html

Regards,

Adzim