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Understanding Additional IP Interface Signals

Honored Contributor II



I'm following this tutorial: http://zhehaomao.com/blog/fpga/2013/12/27/sockit-3.html and have some problems in understanding the final step. Since I think, the signals which I don't understand come from an IP component (hard processor system), I post this under IP component - though, I'm quite unsure where to place it correctly. 


In the first parts, the author shows some Verilog objects to make the Sockit board's LEDs blink. By input of a button, the blink frequency can be increased or decreased. In this 3rd part, the author creates a small design for the same purpose, but now using Qsys. There are the standard "clock", a "hard processor system" and the customized component using the underlying verilog file. Under QSYS then the qsys output file is created and added to the project. Now the top level file, needs some adaptations, such as additional singals for output and inout to handle - why?  


Under "Adding Qsys System to Quartus Project", in the tutorial. the author extends the initially proposed "module" declaration of the first parts: 

module sockit_test ( input CLOCK_50, input KEY, output LED ); 


...by the following new declaration which contains a fair list of new signals, starting by hps_memory_mem* 


module sockit_test ( input CLOCK_50, input KEY, output LED, // HPS memory controller ports output hps_memory_mem_a, output hps_memory_mem_ba, output hps_memory_mem_ck, output hps_memory_mem_ck_n, output hps_memory_mem_cke, output hps_memory_mem_cs_n, output hps_memory_mem_ras_n, output hps_memory_mem_cas_n, output hps_memory_mem_we_n, output hps_memory_mem_reset_n, inout hps_memory_mem_dq, inout hps_memory_mem_dqs, inout hps_memory_mem_dqs_n, output hps_memory_mem_odt, output hps_memory_mem_dm, input hps_memory_oct_rzqin ); 


I'm now trying to port a similar implementation with to different board, as a small starting project. The hps_memory_mem* listed signals here, seem to fall from off the sky. Perhaps, someone with a bit more experience on FPGAs, could give me some hints on that. 


Question: How to obtain these needed additional signals? I mean, is it possible in quartus to see these signals, needed for the .qsys component? Or, are such things mentioned in the datasheet of the board / processor? Or do they depend on the kind of qsys processor component, means if I choose a different, e.g. a NIOS II, then I would need different signals? Which ones?
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Honored Contributor II


I think I found the specific signal interface to my hard processor system. I figured out that QSYS seems to generate also a .bsf file, which can be opened, and within this block assistent the specificly required signals can be read out.  

The second mistake I did, initiallly - working with 2 .vhd files only - I made a third .vhd file as top level description. When made the component under QSYS, including one of the 2 .vhd files, the resulting .qip component got another different name, which I did not update in the top level .vhd file. I still refered to the .vhd file, which was actually inside the .qip.
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