Unified FFT giving incorrect output

[David32]

I have simulated the parallel unified FFT and cannot, in any configuration, get it to output sensible signals. On the other hand, the single, normal, unified FFT simulates correctly.

In an effort to debug this problem:

I configured a PARALLEL Unified FFT as follows:

• Inverse FFT - No
• Bit reversed input = Yes
• Log2Size = 6
• Log2Wires = 1
• Serial stages = 0
• Data = fixed
• reset = high
• input width = 8
• twiddle = 12
• pruning = full word growth (output width = 15)

Also created a Bit reverse IP which generates the input to both a single and parallel (2 channels) FFT:

• Complex = No
• Log2Size = 6
• Input width= 16

Since the parallel FFT requires two input channels (each real/imag) I concatenate the BR output twice to create the required input.

I can send source code and test bench if desired.

I have consulted the User Guide ug20304-683366-787799.pdf many times and cannot see anything that I am doing incorrectly.

Please help with this.

[LeoFeng]

Hi David,

This is Leo, I will help you with your issue.

Can I have your source code and test bench? I will have a look at it and do a simulation with it if necessary.

Also please tell me the Quartus version and the devices that you are using now.

Thank you!

Best regards,

Leo

[David32]

Hi Leo,

I am using:

Quartus Prime 23.4.0 build 79 11/22/2023 SC Pro Edition (Linux)

QuestaSim Intel Starter FPGA Edition-64, Version 2023.3 linux_x86_64

The IP, SRC and Testbench is attached.

Thank you,

David

[David32]

Hi Leo,

Please tell me the status of your simulation.

We need a solution here quite urgently.

Thanks

David