Hi all,For my project, I plan to use an EPCS1SI8N as an EEPROM memory for keeping data and only that. (I have another EPCS to program my FPGA). After launching the FPGA, it has two read (op code 0000.0011 + good address) two words of 32 bits, each one in a different sector (addresses a correctly managed). When I send a special command, I erase (op code 1101.1000 + correct address) the targeted sector (after a write enable code op code 0000.0110) and then write (op code 0000.0010) my new 32 bits's word in the correct address (after another write enable). My state machine seems ok, I checked all state on a scope after verifying many times my states and timing. But for a strange reason, it doesn't work :( I really need help because I have a deadline to respect You can find my code in attachment (it's a VHDL one), I don't use SOPC at all and prefer not use alt_asmi_parallel from wizard Thanks in advance for your help or advice HT86
I watched the code opeartion in a simulation and found that the asdi timing is not according to the SPI mode 0 or 3 requirements. Please read the Altera EPCS or third party SPI flash datasheets (e.g. Numonyx M25P10) thoroughly. ASDI has to be set before the rising DCLK edge, usually it's set on falling edge. There may be more issues, but the code can't work with the present SPI timing.