User MSI generation with DMA enabled

[andrecap]

Hi,

I'm having trouble in generating an MSI in my Endpoint FPGA.
I am using Cyclone 10 GX with "Hard IP for PCI Express"(Avalon-MM) and DMA support.
The MSI is already working when a DMA transaction completes, but I want to send another one defined by the application logic.
I tried to use the Avalon-MM to PCI Express Mailbox Registers (0x3A00) and the Avalon-MM to PCI Express Interrupt Enable Register (0x0050) from CRA, but I don't receive any MSI at the RootPort site.
It also seems that the IER cannot be accessed in WRITE mode.

Some notes:
- MSI is enabed in configuration space.
lspci interesting lines:
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Capabilities: [50] MSI: Enable+ Count=1/4 Maskable- 64bit+

- CRA is enabled. There are no IRQ signals coming out of the CRA interface (but there should be as specified in 8.2 of the ug_a10_pcie_avmm).

Do you have any suggestions?

Regards,

Andrea

[Rahul_S_Intel1]

Have you tried any of example design or you have tried from your own logic

[andrecap]

Hi Rahul,

Thanks for your reply.

we are building our own logic from scratch.
The FPGA is placed on a hardware board we are also developing.

I am writing into the registers from the Root Complex, and I can verify the CRA registers are written correctly through signal tap.

Is it possible that I am getting something wrong in the procedure?

Regards,

Andrea

[Rahul_S_Intel1]

Hi , 

Taking the conversation to private