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Altera_Forum
Honored Contributor I
1,068 Views

Using Stratix V Transceiver native PHY core in the place of Arriai V PHY core

Hi All, 

Is it possible to directly replace the Transceiver native PHY core of Arria V GZ with Stratix V Transceiver native PHY core? If so how can it be implemented. Though its been stated Arria V GZ supports only maximum of 9.9Gbps Standard PCS it can be further extended with Stratix IP to 12.5 Gbps. I tried manually instantiating the IP and synthesize was successful whereas the fitter found error stating that the output frequency exceeds that of the current device grade's maximum. 

 

Thanks inadvance
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10 Replies
Altera_Forum
Honored Contributor I
29 Views

Could you please clarify what you are trying to do? 

 

Are you trying to place-and-route a design for an Arria V GZ or for a Stratix V? Or are you just trying to figure out which FPGA to use? 

 

There are three PCS modes; skip it, Standard PCS, and 10G PCS. Which ones have you tried? What is it that you are trying to do? 

 

I've been testing with the Arria V GZ on the Texas Instruments TSW14J56 board, and have tested various PHY setups at up to 10Gbps. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
29 Views

Hi Dave, 

 

The actual scenario is altera had suggested a override wherein we can use a Stratix V transceiver IP(soft PCS) in a Arria V Gz device. This override will allow us to reach speed more than 10Gbps in Arria V Gz with standard soft PCS(SV soft PCS). The usual Arria V Gz transceiver with Soft PCS(standard) has been limited only till 9.9Gbps. I would like to know if this solution is applicable. Whether one device like Startix IP can be migrated to Arria??
Altera_Forum
Honored Contributor I
29 Views

 

--- Quote Start ---  

 

The actual scenario is altera had suggested a override wherein we can use a Stratix V transceiver IP(soft PCS) in a Arria V Gz device. This override will allow us to reach speed more than 10Gbps in Arria V Gz with standard soft PCS(SV soft PCS). The usual Arria V Gz transceiver with Soft PCS(standard) has been limited only till 9.9Gbps. I would like to know if this solution is applicable. Whether one device like Startix IP can be migrated to Arria?? 

--- Quote End ---  

 

You do not need an over-ride, just instantiate the PHY in direct mode (no PCS) or use the 10G PCS. They both work fine. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
29 Views

 

--- Quote Start ---  

You do not need an over-ride, just instantiate the PHY in direct mode (no PCS) or use the 10G PCS. They both work fine. 

 

Cheers, 

Dave 

--- Quote End ---  

 

 

Hi Dave, 

Yes that would help but I intend to retain the rest of the design to be the same and do not want major changes. When I consulted with Altera they suggested the above quoted solution if I intend to go with the standard PCS. I am waiting for their response meanwhile wanted to know if some one already tried it. 

 

Thanks 

Gowtham
Altera_Forum
Honored Contributor I
29 Views

 

--- Quote Start ---  

 

Yes that would help but I intend to retain the rest of the design to be the same and do not want major changes. When I consulted with Altera they suggested the above quoted solution if I intend to go with the standard PCS. I am waiting for their response meanwhile wanted to know if some one already tried it. 

 

--- Quote End ---  

 

If you look at the hierarchy in your synthesized design, you will see that the components are named with sv_xxx or xxx_sv, where sv = Stratix V, i.e., the Arria V GZ transceivers match those on the Stratix V. Altera's suggestion implies there is probably an over-ride option for the "allowable range of data rates" rather than actually changing the IP core, since the cores appear to be the same for both of these devices. 

 

Unfortunately I have never heard of that over-ride, sorry. 

 

What 10Gbps interfaces are you working with? I'm trying to get some QSFP+ links working. I can get nice clean eye patterns for internal loopback mode at 10Gbps, but any "real-world" tests have not been very successful. I suspect the hardware I have is not up to the task, i.e., a Texas Instruments TSW14J56 Arria V GZ board with FMC connector and a VadaTech FMC108 FMC-to-QSFP+ with Vitesse redriver PHYs. If your hardware happens to have QSFP+ connectors, or 10Gbps on SMA connectors, I'd be interested in seeing some eye-pattern sweeps created using the Transceiver Toolkit. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
29 Views

 

--- Quote Start ---  

If you look at the hierarchy in your synthesized design, you will see that the components are named with sv_xxx or xxx_sv, where sv = Stratix V, i.e., the Arria V GZ transceivers match those on the Stratix V. Altera's suggestion implies there is probably an over-ride option for the "allowable range of data rates" rather than actually changing the IP core, since the cores appear to be the same for both of these devices. 

 

Unfortunately I have never heard of that over-ride, sorry. 

 

What 10Gbps interfaces are you working with? I'm trying to get some QSFP+ links working. I can get nice clean eye patterns for internal loopback mode at 10Gbps, but any "real-world" tests have not been very successful. I suspect the hardware I have is not up to the task, i.e., a Texas Instruments TSW14J56 Arria V GZ board with FMC connector and a VadaTech FMC108 FMC-to-QSFP+ with Vitesse redriver PHYs. If your hardware happens to have QSFP+ connectors, or 10Gbps on SMA connectors, I'd be interested in seeing some eye-pattern sweeps created using the Transceiver Toolkit. 

 

Cheers, 

Dave 

--- Quote End ---  

 

 

Hi Dave, 

I am actually trying to make the Arria V Gz transceivers work above 10 Gbps with standard PCS. I dont have QSFP+ connector or have equipment to observe eye pattern. There is an option to enable the eyeQ in the transceiver reconfiguration which I am yet to implement. 

 

Thanks, 

Gowtham
Altera_Forum
Honored Contributor I
29 Views

 

--- Quote Start ---  

 

I am actually trying to make the Arria V Gz transceivers work above 10 Gbps with standard PCS. 

 

--- Quote End ---  

 

Why? What feature does the Standard PCS have that the 10G PCS does not? 

 

 

--- Quote Start ---  

 

I dont have QSFP+ connector or have equipment to observe eye pattern. There is an option to enable the eyeQ in the transceiver reconfiguration which I am yet to implement. 

 

--- Quote End ---  

 

Ok. The Transceiver Toolkit is useful ... though a little buggy in 14.0. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
29 Views

 

--- Quote Start ---  

Why? What feature does the Standard PCS have that the 10G PCS does not? 

 

--- Quote End ---  

 

 

There are certain transceiver core IP output signals which cannot be utilized in 10 G mode like datakchar which I am using currently in standard PCS mode. These essential signals automatically disappear when I select 10G mode and standard PCS.
Altera_Forum
Honored Contributor I
29 Views

 

--- Quote Start ---  

There are certain transceiver core IP output signals which cannot be utilized in 10 G mode like datakchar which I am using currently in standard PCS mode. These essential signals automatically disappear when I select 10G mode and standard PCS. 

--- Quote End ---  

 

Ok, that makes sense. 

 

I'm not sure if you know this, but you can lie to Quartus :) 

 

For example, lets say you nominally use a 125MHz reference and configure the IP for 125MHz x 64 = 8000Mbps lanes. If the 125MHz reference is programmable, eg., you have a synthesizer connected to the REFCLK input via an SMA connector, then you can program the synthesizer for 156.25MHz and the PHY will operate at 10Gbps just fine. How can you tell its working? You use the Transceiver Toolkit and check the eye pattern sweep in loopback mode. If you're not getting errors, then things appear to be working. To determine the range of frequencies over which this lie works, I'll run the transceiver toolkit loopback test, modify the synthesizer frequency slightly (+10MHz), clear bit-errors and then wait to see if there are bit errors at this new setting. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
29 Views

 

--- Quote Start ---  

Ok, that makes sense. 

 

I'm not sure if you know this, but you can lie to Quartus :) 

 

For example, lets say you nominally use a 125MHz reference and configure the IP for 125MHz x 64 = 8000Mbps lanes. If the 125MHz reference is programmable, eg., you have a synthesizer connected to the REFCLK input via an SMA connector, then you can program the synthesizer for 156.25MHz and the PHY will operate at 10Gbps just fine. How can you tell its working? You use the Transceiver Toolkit and check the eye pattern sweep in loopback mode. If you're not getting errors, then things appear to be working. To determine the range of frequencies over which this lie works, I'll run the transceiver toolkit loopback test, modify the synthesizer frequency slightly (+10MHz), clear bit-errors and then wait to see if there are bit errors at this new setting. 

 

Cheers, 

Dave 

--- Quote End ---  

 

 

Thanks Dave I will try this and see if I can get it working.
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