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Altera_Forum
Honored Contributor I
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Using rx_st_err in Stratix V Hard IP for PCI Express

I read in the documentation that when an uncorrectable ECC error occurs the Application layer should reset the Hard IP. That sounds a bit drastic as there could be other incomming packets, TLPs being sent in the TX path, and there is also all the information inside the configuration registers, set by the root port. 

 

Does anyone know what gets reset and what doesn't? I presume the configuration registers do not get reset, but that is just a guess. 

 

Is there a way to know if there is something pending in the TX buffers? I presume the correct procedure here would be: 

- take rx_st_ready low to stop incomming packets 

- stop transmitting packets 

- wait until the TX buffer is free 

- issue the reset, then resume. 

Any killed completions would timeout. I just hope posted packets from the outside would be resent somehow. 

 

What do you think?
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