Honored Contributor II
07-01-2015 03:45 PM
Hello all,I have a QSys made SoC consisting of a NIOS II/f, which is connected to several peripherals including an Altera VIC, which accepts 3 different interrupts. I think the Avalon Bus interconnection is done correctly and all interrupt lines are connected to the VIC. The VIC has 7 shadow register sets enabled, where 3 of them correspond to the mentioned interrupt contexts (set in the BSP editor, if I remember correctly). All modules are driven with a clock frequency of 75 MHz created via the PLL V module outside the QSys SoC. It is important to mention, that one of these interrupts (with the highest priority and enabled to preempt the others) occures with a high frequency. The time between the interrupts is 40µs approximately. It triggers the step function of a discrete controller implemented in software on the NIOS. This step function consumes around 10µs of this time, so there should plenty of time be left for context switching. I now encounter an interesting issue. Some of the interrupts are missed. This has been observed via SignalTap and an oscilloscope. It also seems to be that with increasing program complexity more interrupts are missed. Even if the other 2 interrupts are disabled and even disconnected (including JTAG UART) still some interrupts of the remaining module are missed. This critical interrupt is triggered via a PIO module, which happens reliably as seen in SignalTap. Therefor, the error source must be within the VIC or NIOS. The program code is written bare metal in C using the Altera API for hardware access and configuration. I have studied all documents concerning the VIC core and have followed all instructions for registration of the interrupts. The whole system is used to control an electrical drive. Nevertheless, EMC has already been excluded as error source to cause the issue. Is this a common issue? Has someone documented problems, where interrupts are missed using the VIC? Could this be related to context switching problems? Is it even possible (in a practical way), that interrupts are sometimes omitted using the VIC with NIOS? I appreciate all help. Thank you very much!