FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
The Intel sign-in experience has changed to support enhanced security controls. If you sign in, click here for more information.
6153 Discussions

VIP 9.1SP2 Clipper Misbehaviour?

Honored Contributor II

Hi All, 


I am having a bit of trouble with the clipper.  


Where does it get the output packet format from? 

The registers? The input packet format? I have sensible register values loaded, sensible data going in, but the output packet size in the header seems bogus, and I don't know why. 


My system: 


CTI -> CRS -> CSC -> CLIP -> SCL -> FB -> CTO 


I have HD video (1080i/59.94) coming into the CTI, parallel Y/C @ 74.xxMHz, 16 bit wide. 


CTI is locked, and reporting sensible values for pixel count etc. 

I have programmed the clipper to clip to the region (1,1) -> (0x700, 0x210). 


In the sim, I see sensible packets going into the clipper (looking at the 0x0F type packet header, I get 0x00000F, 0x080700, 0x020000, 0x0A0C01, so that's 0x780/1920 wide, 0x21C/540 high, interlaced). 


At the output of the clipper, I get two "packet format" packets, the first is a duplicate of the input (0x00000F, 0x080700, 0x020000, 0x0A0C01) and the second is different (0x00000F, 0x070000, 0x00000F, 0x0A0B00, i.e. 0x7F wide, 0x0B high?).  


My registers into the clipper are  

2 <= 0x00000001 

3 <= 0x00000700 

4 <= 0x00000001 

5 <= 0x00000210 


I have no idea where the clipper is getting the output packet size fields from. This is in simulation, it goes without saying that it isn't working properly in silicon either. 


Any hints? Any body had similar experiences? 


0 Kudos
1 Reply
Honored Contributor II

After some more poking around on the bench ... in the SOPC GUI, the "rectangle" and "offset" option was incorrect. All OK now.